Commit Graph

5 Commits

Author SHA1 Message Date
Mikhail Maltsev 4388e8f820 [Targets] Implement getConstraintRegister for ARM and AArch64
Summary:
The getConstraintRegister method is used by semantic checking of
inline assembly statements in order to diagnose conflicts between
clobber list and input/output lists. Currently ARM and AArch64 don't
override getConstraintRegister, so conflicts between registers
assigned to variables in asm labels and clobber lists are not
diagnosed. Such conflicts can cause assertion failures in the back end
and even miscompilations.

This patch implements getConstraintRegister for ARM and AArch64
targets. Since these targets don't have single-register constraints,
the implementation is trivial and just returns the register specified
in an asm label (if any).

Reviewers: eli.friedman, javed.absar, thopre

Reviewed By: thopre

Subscribers: rengolin, eraman, rogfer01, myatsina, kristof.beyls, cfe-commits, chrib

Differential Revision: https://reviews.llvm.org/D45965

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@331164 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-30 09:11:08 +00:00
Akira Hatanaka dfc0ac7f3d [AArch64, inline-asm] Improve diagnostic that is printed when the size of a
variable that has regiser constraint "r" is not 64-bit.

General register operands are output using 64-bit "x" register names, regardless
of the size of the variable, unless the asm operand is prefixed with the "%w"
modifier. This surprises and confuses many users who aren't familiar with
aarch64 inline assembly rules.

With this commit, a note and fixit hint are printed which tell the users that
they need modifier "%w" in order to output a "w" register instead of an "x"
register.

<rdar://problem/12764785>


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@216260 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 06:05:21 +00:00
James Molloy 024c76d36d Revert part of r206963
Specifically the part where we removed a warning to be compatible with GCC, which has been widely regarded as a bad idea.

I'm not quite happy with how obtuse this warning is, especially in the fairly common case of a 32-bit integer literal, so I've got another patch awaiting review that adds a fixit to reduce confusion.



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@213935 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-25 10:19:47 +00:00
James Molloy fa203ed5f9 [ARM64] Change inline assembly constraints to be more lax, to match the behaviour of Clang/AArch64 and GCC.
GCC allows sub-64bit values to use the 'r' register constraint.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@206963 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 10:26:19 +00:00
Tim Northover 7e0e8ef787 ARM64: initial clang support commit.
This adds Clang support for the ARM64 backend. There are definitely
still some rough edges, so please bring up any issues you see with
this patch.

As with the LLVM commit though, we think it'll be more useful for
merging with AArch64 from within the tree.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@205100 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 15:09:45 +00:00