Commit Graph

31 Commits

Author SHA1 Message Date
Sjoerd Meijer e4d319b99a [ARM] Add tests for the vcvtr builtins
This adds Sema and Codegen tests for the vcvtr builtins
(because they were missing).

Differential Revision: https://reviews.llvm.org/D43372


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@325351 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-16 16:01:08 +00:00
Mehdi Amini 7a4550308b IRGen: Add optnone attribute on function during O0
Amongst other, this will help LTO to correctly handle/honor files
compiled with O0, helping debugging failures.
It also seems in line with how we handle other options, like how
-fnoinline adds the appropriate attribute as well.

Differential Revision: https://reviews.llvm.org/D28404

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304127 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-29 05:38:20 +00:00
Chad Rosier 0d9e23af40 [ARM] Use generic bitreverse intrinsic, rather than ARM specific rbit.
The backend already supports lowering this intrinsic to a rbit instruction.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@291582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-10 18:55:11 +00:00
Ranjeet Singh ddd8ec8463 [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.
Reapplying patch in r272777 which was reverted
because the llvm patch which added support
for generating the mcrr/mcrr2 instructions
from the intrinsic was causing an assertion
failure. This has now been fixed in llvm.



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@272983 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-17 00:59:41 +00:00
Ranjeet Singh e03851aea2 Reverting r272777 because one of the tests
added in the llvm patch is causing an assertion
to fail.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@272790 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-15 14:21:28 +00:00
Ranjeet Singh c39587a0d1 [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.
Patch adds intrinsics for mrrc/mrrc2. The
intrinsics for mrrc/mrrc2 return a single
uint64_t to represent two 32 bit values.

The mcrr/mcrr2 intrinsic was changed to
accept a single uint64_t instead of two
32 bit values as the input for consistency.

Differential Revision: http://reviews.llvm.org/D21179



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@272777 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-15 11:32:18 +00:00
Ranjeet Singh 6358954832 [ARM] Add load/store co-processor intrinsics.
Differential Revision: http://reviews.llvm.org/D20563



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@271275 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 13:31:25 +00:00
Ranjeet Singh f62f895515 [ARM] Fix cdp intrinsic
- Fixed cdp intrinsic to only accept compile time
  constant values previously you could pass in a
  variable to the builtin which would result in
  illegal llvm assembly output

Differential Revision: http://reviews.llvm.org/D20394



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@270058 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-19 13:04:34 +00:00
Tim Northover 0ca63760b6 ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.
This is mostly a one-time autoconversion of tests that checked assembly after
"-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This
should make them much more stable to changes in LLVM so they won't break on
unrelated changes.

"opt -mem2reg" is a compromise designed to increase the readability of tests
that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is
stable enough that no surpises will come along.

Should address http://llvm.org/PR26815.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@263048 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-09 18:54:42 +00:00
Ahmed Bougacha 089703e731 [ARM] Mark mcr/mrc builtin operands as required-immediate.
An early error message is better than the "cannot select" alternative.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@246094 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-26 22:21:07 +00:00
Luke Cheeseman 514068cf49 This patch implements clang support for the ACLE special register intrinsics
in section 10.1, __arm_{w,r}sr{,p,64}.

This includes arm_acle.h definitions with builtins and codegen to support
these, the intrinsics are implemented by generating read/write_register calls
which get appropriately lowered in the backend based on the register string
provided. SemaChecking is also implemented to fault invalid parameters.

Differential Revision: http://reviews.llvm.org/D9697



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@239737 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 17:51:01 +00:00
Yi Kong 982f0de813 ARM: Add dbg builtin intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@216452 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-26 12:48:06 +00:00
Justin Bogner 11f792a2b3 test/CodeGen: Don't rely on a value's number in check lines
The tests in r215568 hard code a value as %0 in their checks. This
isn't correct in asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@215585 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-13 21:54:06 +00:00
Yi Kong e68984a0fe ARM: Prefetch intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@215568 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-13 19:18:14 +00:00
Yi Kong dbc52fa0e2 ARM: Implement __builtin_arm_nop intrinsic
This patch implements __builtin_arm_nop intrinsic for AArch32 and AArch64,
which generates hint 0x0, the alias of NOP instruction.

This intrinsic is necessary to implement ACLE __nop intrinsic.

Differential Revision: http://reviews.llvm.org/D4495


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@212947 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 15:20:09 +00:00
Yi Kong 57e6028e91 [ARM] Implement ISB memory barrier intrinsic
Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions
modelling by adding has-side-effects property.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@212277 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-03 16:01:25 +00:00
Saleem Abdulrasool 512e9c089c ARM: rename ARM builtins to use __builtin_arm prefix
This corrects SVN r212196's naming change to use the proper prefix of
`__builtin_arm_` instead of `__builtin_`.

Thanks to Yi Kong for pointing out the incorrect naming!

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@212253 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-03 02:43:20 +00:00
Saleem Abdulrasool 38b6a39b0e CodeGen: make target builtins support languages
This extends the target builtin support to allow language specific annotations
(i.e. LANGBUILTIN).  This is to allow MSVC compatibility whilst retaining the
ability to have EABI targets use a __builtin_ prefix.  This is merely to allow
uniformity in the EABI case where the unprefixed name is provided as an alias in
the header.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@212196 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 17:41:27 +00:00
Jim Grosbach 16c0c02b2f ARM: Support for __builtin_arm_rbit() intrinsic.
Reverse the bits in a word. Maps to the RBIT instruction.

rdar://9283021

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@211059 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-16 21:55:58 +00:00
Saleem Abdulrasool b25d6195cc CodeGen: complete ARM ACLE hint 8.4 support
Add support for the remaining hints from the ACLE.  Although __dbg is listed as
a hint, it is handled different, so it is not covered by this change.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@207930 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-04 02:52:25 +00:00
Saleem Abdulrasool 0f870bf174 CodeGen: rename __builtin_arm_sevl to __sevl
ACLE adds the __sevl() extension.  Rename the hint from a custom name to the
ACLE specified name.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@207829 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 06:53:57 +00:00
Saleem Abdulrasool 653f5c673b CodeGen: replace use of @llvm.arm.sevl with @llvm.arm.hint
Use the new generic @llvm.arm.hint hint intrinsic rather than the specialised
@llvm.arm.sevl hint instruction.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@207243 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 17:25:46 +00:00
Weiming Zhao 186b26d01f add intrinsics: __builtin_arm_{dmb,dsb} for ARM
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@194513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:42:50 +00:00
Joey Gouly 594e193073 [ARM] Add a builtin to allow you to use the 'sevl' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@191816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-02 10:00:18 +00:00
Logan Chien a8f7a97a22 Implement __builtin_eh_return_data_regno() for ARM and MIPS.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@175954 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-23 04:24:36 +00:00
Jim Grosbach f794705837 Tests: check for target availability for target-specific tests.
Lots of tests are using an explicit target triple w/o first checking that the
target is actually available. Add a REQUIRES clause to a bunch of them. This should
hopefully unbreak bots which don't configure w/ all targets enabled.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@159949 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09 18:34:21 +00:00
Daniel Dunbar 1058253c36 Builtins/ARM: __clear_cache doesn't seem to have a consistent prototype, declare
the builtin as void __clear_cache(...) to workaround this, which appears to
match what GCC does.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@108487 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 00:31:23 +00:00
Rafael Espindola a71d3c6537 Add a test to the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@105596 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 03:59:28 +00:00
John McCall 468ec6c026 Revert changes r97693, r97700, and r97718.
Our testing framework can't deal with disabled targets yet.



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@97719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 04:29:44 +00:00
John McCall 3ff63027f6 XFAIL these tests on win32, since the win32 buildbot apparently disables all
targets except X86.



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@97718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 04:14:44 +00:00
Chris Lattner 2752c0137d add framework for ARM builtins, Patch by Edmund Grimley Evans!
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@97656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 19:03:45 +00:00