Summary:
Named registers with the constraint "=&r" currently lose the early clobber flag
and turn into "=r" when converted to LLVM-IR. This patch correctly passes it on.
Reviewers: atanasyan
Reviewed By: atanasyan
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D7346
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@228143 91177308-0d34-0410-b5e6-96231b3b80d8
Lots of tests are using an explicit target triple w/o first checking that the
target is actually available. Add a REQUIRES clause to a bunch of them. This should
hopefully unbreak bots which don't configure w/ all targets enabled.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@159949 91177308-0d34-0410-b5e6-96231b3b80d8
register constraint. Note that we're not checking if the register itself
is valid for the constraint.
Fixes rdar://9382985
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@133226 91177308-0d34-0410-b5e6-96231b3b80d8
Daniel Sanders