mirror of https://github.com/microsoft/clang.git
Promote storage-only __fp16 vector operands to float vectors.
This commit fixes a bug in the handling of storage-only __fp16 vectors where clang didn't promote __fp16 vector operands to float vectors. Conceptually, it performs the following transformation on the AST in CreateBuiltinBinOp and CreateBuiltinUnaryOp: (Before) typedef __fp16 half4 __attribute__ ((vector_size (8))); typedef float float4 __attribute__ ((vector_size (16))); half4 hv0, hv1, hv2, hv3; hv0 = hv1 + hv2 + hv3; (After) float4 t0 = (float4)hv1 + (float4)hv2; float4 t1 = t0 + (float4)hv3; hv0 = (half4)t1; Note that this commit fixes the bug for targets that set HalfArgsAndReturns to true (ARM and ARM64). Targets using intrinsics such as llvm.convert.to.fp16 to handle __fp16 are still broken. rdar://problem/20625184 Differential Revision: https://reviews.llvm.org/D32520 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@314056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
2e4086bb2d
commit
d0d150d713
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@ -1014,10 +1014,41 @@ Value *ScalarExprEmitter::EmitScalarConversion(Value *Src, QualType SrcType,
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return Builder.CreateVectorSplat(NumElements, Src, "splat");
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}
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// Allow bitcast from vector to integer/fp of the same size.
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if (isa<llvm::VectorType>(SrcTy) ||
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isa<llvm::VectorType>(DstTy))
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return Builder.CreateBitCast(Src, DstTy, "conv");
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if (isa<llvm::VectorType>(SrcTy) || isa<llvm::VectorType>(DstTy)) {
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// Allow bitcast from vector to integer/fp of the same size.
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unsigned SrcSize = SrcTy->getPrimitiveSizeInBits();
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unsigned DstSize = DstTy->getPrimitiveSizeInBits();
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if (SrcSize == DstSize)
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return Builder.CreateBitCast(Src, DstTy, "conv");
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// Conversions between vectors of different sizes are not allowed except
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// when vectors of half are involved. Operations on storage-only half
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// vectors require promoting half vector operands to float vectors and
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// truncating the result, which is either an int or float vector, to a
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// short or half vector.
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// Source and destination are both expected to be vectors.
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llvm::Type *SrcElementTy = SrcTy->getVectorElementType();
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llvm::Type *DstElementTy = DstTy->getVectorElementType();
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assert(((SrcElementTy->isIntegerTy() &&
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DstElementTy->isIntegerTy()) ||
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(SrcElementTy->isFloatingPointTy() &&
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DstElementTy->isFloatingPointTy())) &&
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"unexpected conversion between a floating-point vector and an "
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"integer vector");
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// Truncate an i32 vector to an i16 vector.
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if (SrcElementTy->isIntegerTy())
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return Builder.CreateIntCast(Src, DstTy, false, "conv");
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// Truncate a float vector to a half vector.
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if (SrcSize > DstSize)
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return Builder.CreateFPTrunc(Src, DstTy, "conv");
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// Promote a half vector to a float vector.
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return Builder.CreateFPExt(Src, DstTy, "conv");
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}
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// Finally, we have the arithmetic types: real int/float.
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Value *Res = nullptr;
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@ -7503,6 +7503,14 @@ Sema::CheckAssignmentConstraints(SourceLocation Loc,
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return CheckAssignmentConstraints(LHSType, RHSPtr, K, /*ConvertRHS=*/false);
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}
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/// This helper function returns true if QT is a vector type that has element
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/// type ElementType.
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static bool isVector(QualType QT, QualType ElementType) {
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if (const VectorType *VT = QT->getAs<VectorType>())
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return VT->getElementType() == ElementType;
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return false;
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}
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/// CheckAssignmentConstraints (C99 6.5.16) - This routine currently
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/// has code to accommodate several GCC extensions when type checking
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/// pointers. Here are some objectionable examples that GCC considers warnings:
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@ -8131,6 +8139,25 @@ static bool tryVectorConvertAndSplat(Sema &S, ExprResult *scalar,
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return false;
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}
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/// Convert vector E to a vector with the same number of elements but different
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/// element type.
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static ExprResult convertVector(Expr *E, QualType ElementType, Sema &S) {
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const auto *VecTy = E->getType()->getAs<VectorType>();
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assert(VecTy && "Expression E must be a vector");
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QualType NewVecTy = S.Context.getVectorType(ElementType,
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VecTy->getNumElements(),
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VecTy->getVectorKind());
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// Look through the implicit cast. Return the subexpression if its type is
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// NewVecTy.
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if (auto *ICE = dyn_cast<ImplicitCastExpr>(E))
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if (ICE->getSubExpr()->getType() == NewVecTy)
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return ICE->getSubExpr();
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auto Cast = ElementType->isIntegerType() ? CK_IntegralCast : CK_FloatingCast;
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return S.ImpCastExprToType(E, NewVecTy, Cast);
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}
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/// Test if a (constant) integer Int can be casted to another integer type
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/// IntTy without losing precision.
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static bool canConvertIntToOtherIntTy(Sema &S, ExprResult *Int,
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@ -11465,6 +11492,41 @@ static NamedDecl *getDeclFromExpr(Expr *E) {
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return nullptr;
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}
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// This helper function promotes a binary operator's operands (which are of a
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// half vector type) to a vector of floats and then truncates the result to
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// a vector of either half or short.
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static ExprResult convertHalfVecBinOp(Sema &S, ExprResult LHS, ExprResult RHS,
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BinaryOperatorKind Opc, QualType ResultTy,
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ExprValueKind VK, ExprObjectKind OK,
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bool IsCompAssign, SourceLocation OpLoc,
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FPOptions FPFeatures) {
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auto &Context = S.getASTContext();
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assert((isVector(ResultTy, Context.HalfTy) ||
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isVector(ResultTy, Context.ShortTy)) &&
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"Result must be a vector of half or short");
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assert(isVector(LHS.get()->getType(), Context.HalfTy) &&
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isVector(RHS.get()->getType(), Context.HalfTy) &&
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"both operands expected to be a half vector");
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RHS = convertVector(RHS.get(), Context.FloatTy, S);
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QualType BinOpResTy = RHS.get()->getType();
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// If Opc is a comparison, ResultType is a vector of shorts. In that case,
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// change BinOpResTy to a vector of ints.
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if (isVector(ResultTy, Context.ShortTy))
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BinOpResTy = S.GetSignedVectorType(BinOpResTy);
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if (IsCompAssign)
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return new (Context) CompoundAssignOperator(
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LHS.get(), RHS.get(), Opc, ResultTy, VK, OK, BinOpResTy, BinOpResTy,
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OpLoc, FPFeatures);
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LHS = convertVector(LHS.get(), Context.FloatTy, S);
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auto *BO = new (Context) BinaryOperator(LHS.get(), RHS.get(), Opc, BinOpResTy,
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VK, OK, OpLoc, FPFeatures);
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return convertVector(BO, ResultTy->getAs<VectorType>()->getElementType(), S);
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}
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static std::pair<ExprResult, ExprResult>
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CorrectDelayedTyposInBinOp(Sema &S, BinaryOperatorKind Opc, Expr *LHSExpr,
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Expr *RHSExpr) {
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@ -11485,6 +11547,14 @@ CorrectDelayedTyposInBinOp(Sema &S, BinaryOperatorKind Opc, Expr *LHSExpr,
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return std::make_pair(LHS, RHS);
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}
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/// Returns true if conversion between vectors of halfs and vectors of floats
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/// is needed.
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static bool needsConversionOfHalfVec(bool OpRequiresConversion, ASTContext &Ctx,
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QualType SrcType) {
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return OpRequiresConversion && !Ctx.getLangOpts().NativeHalfType &&
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Ctx.getLangOpts().HalfArgsAndReturns && isVector(SrcType, Ctx.HalfTy);
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}
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/// CreateBuiltinBinOp - Creates a new built-in binary operation with
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/// operator @p Opc at location @c TokLoc. This routine only supports
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/// built-in operations; ActOnBinOp handles overloaded operators.
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@ -11516,6 +11586,7 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
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QualType CompResultTy; // Type of computation result
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ExprValueKind VK = VK_RValue;
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ExprObjectKind OK = OK_Ordinary;
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bool ConvertHalfVec = false;
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std::tie(LHS, RHS) = CorrectDelayedTyposInBinOp(*this, Opc, LHSExpr, RHSExpr);
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if (!LHS.isUsable() || !RHS.isUsable())
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@ -11567,6 +11638,7 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
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break;
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case BO_Mul:
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case BO_Div:
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ConvertHalfVec = true;
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ResultTy = CheckMultiplyDivideOperands(LHS, RHS, OpLoc, false,
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Opc == BO_Div);
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break;
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@ -11574,9 +11646,11 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
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ResultTy = CheckRemainderOperands(LHS, RHS, OpLoc);
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break;
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case BO_Add:
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ConvertHalfVec = true;
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ResultTy = CheckAdditionOperands(LHS, RHS, OpLoc, Opc);
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break;
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case BO_Sub:
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ConvertHalfVec = true;
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ResultTy = CheckSubtractionOperands(LHS, RHS, OpLoc);
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break;
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case BO_Shl:
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@ -11587,10 +11661,12 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
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case BO_LT:
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case BO_GE:
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case BO_GT:
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ConvertHalfVec = true;
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ResultTy = CheckCompareOperands(LHS, RHS, OpLoc, Opc, true);
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break;
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case BO_EQ:
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case BO_NE:
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ConvertHalfVec = true;
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ResultTy = CheckCompareOperands(LHS, RHS, OpLoc, Opc, false);
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break;
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case BO_And:
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@ -11602,10 +11678,12 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
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break;
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case BO_LAnd:
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case BO_LOr:
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ConvertHalfVec = true;
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ResultTy = CheckLogicalOperands(LHS, RHS, OpLoc, Opc);
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break;
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case BO_MulAssign:
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case BO_DivAssign:
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ConvertHalfVec = true;
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CompResultTy = CheckMultiplyDivideOperands(LHS, RHS, OpLoc, true,
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Opc == BO_DivAssign);
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CompLHSTy = CompResultTy;
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@ -11619,11 +11697,13 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
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ResultTy = CheckAssignmentOperands(LHS.get(), RHS, OpLoc, CompResultTy);
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break;
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case BO_AddAssign:
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ConvertHalfVec = true;
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CompResultTy = CheckAdditionOperands(LHS, RHS, OpLoc, Opc, &CompLHSTy);
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if (!CompResultTy.isNull() && !LHS.isInvalid() && !RHS.isInvalid())
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ResultTy = CheckAssignmentOperands(LHS.get(), RHS, OpLoc, CompResultTy);
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break;
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case BO_SubAssign:
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ConvertHalfVec = true;
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CompResultTy = CheckSubtractionOperands(LHS, RHS, OpLoc, &CompLHSTy);
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if (!CompResultTy.isNull() && !LHS.isInvalid() && !RHS.isInvalid())
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ResultTy = CheckAssignmentOperands(LHS.get(), RHS, OpLoc, CompResultTy);
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@ -11656,6 +11736,16 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
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if (ResultTy.isNull() || LHS.isInvalid() || RHS.isInvalid())
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return ExprError();
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// Some of the binary operations require promoting operands of half vector to
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// float vectors and truncating the result back to half vector. For now, we do
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// this only when HalfArgsAndReturn is set (that is, when the target is arm or
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// arm64).
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assert(isVector(RHS.get()->getType(), Context.HalfTy) ==
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isVector(LHS.get()->getType(), Context.HalfTy) &&
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"both sides are half vectors or neither sides are");
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ConvertHalfVec = needsConversionOfHalfVec(ConvertHalfVec, Context,
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LHS.get()->getType());
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// Check for array bounds violations for both sides of the BinaryOperator
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CheckArrayAccess(LHS.get());
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CheckArrayAccess(RHS.get());
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@ -11678,14 +11768,26 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
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dyn_cast<ObjCIvarRefExpr>(LHS.get()->IgnoreParenCasts()))
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DiagnoseDirectIsaAccess(*this, OIRE, OpLoc, RHS.get());
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if (CompResultTy.isNull())
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// Opc is not a compound assignment if CompResultTy is null.
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if (CompResultTy.isNull()) {
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if (ConvertHalfVec)
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return convertHalfVecBinOp(*this, LHS, RHS, Opc, ResultTy, VK, OK, false,
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OpLoc, FPFeatures);
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return new (Context) BinaryOperator(LHS.get(), RHS.get(), Opc, ResultTy, VK,
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OK, OpLoc, FPFeatures);
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}
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// Handle compound assignments.
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if (getLangOpts().CPlusPlus && LHS.get()->getObjectKind() !=
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OK_ObjCProperty) {
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VK = VK_LValue;
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OK = LHS.get()->getObjectKind();
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}
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if (ConvertHalfVec)
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return convertHalfVecBinOp(*this, LHS, RHS, Opc, ResultTy, VK, OK, true,
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OpLoc, FPFeatures);
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return new (Context) CompoundAssignOperator(
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LHS.get(), RHS.get(), Opc, ResultTy, VK, OK, CompLHSTy, CompResultTy,
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OpLoc, FPFeatures);
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@ -12043,6 +12145,7 @@ ExprResult Sema::CreateBuiltinUnaryOp(SourceLocation OpLoc,
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ExprValueKind VK = VK_RValue;
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ExprObjectKind OK = OK_Ordinary;
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QualType resultType;
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bool ConvertHalfVec = false;
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if (getLangOpts().OpenCL) {
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QualType Ty = InputExpr->getType();
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// The only legal unary operation for atomics is '&'.
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@ -12082,6 +12185,16 @@ ExprResult Sema::CreateBuiltinUnaryOp(SourceLocation OpLoc,
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case UO_Minus:
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Input = UsualUnaryConversions(Input.get());
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if (Input.isInvalid()) return ExprError();
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// Unary plus and minus require promoting an operand of half vector to a
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// float vector and truncating the result back to a half vector. For now, we
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// do this only when HalfArgsAndReturns is set (that is, when the target is
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// arm or arm64).
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ConvertHalfVec =
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needsConversionOfHalfVec(true, Context, Input.get()->getType());
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// If the operand is a half vector, promote it to a float vector.
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if (ConvertHalfVec)
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Input = convertVector(Input.get(), Context.FloatTy, *this);
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resultType = Input.get()->getType();
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if (resultType->isDependentType())
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break;
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@ -12219,8 +12332,12 @@ ExprResult Sema::CreateBuiltinUnaryOp(SourceLocation OpLoc,
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if (Opc != UO_AddrOf && Opc != UO_Deref)
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CheckArrayAccess(Input.get());
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return new (Context)
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auto *UO = new (Context)
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UnaryOperator(Input.get(), Opc, resultType, VK, OK, OpLoc);
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// Convert the result back to a half vector.
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if (ConvertHalfVec)
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return convertVector(UO, Context.HalfTy, *this);
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return UO;
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}
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/// \brief Determine whether the given expression is a qualified member
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@ -0,0 +1,162 @@
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// REQUIRES: arm-registered-target
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// RUN: %clang_cc1 -triple arm64-apple-ios9 -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s --check-prefix=CHECK
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// RUN: %clang_cc1 -triple armv7-apple-ios9 -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s --check-prefix=CHECK
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typedef __fp16 half4 __attribute__ ((vector_size (8)));
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typedef short short4 __attribute__ ((vector_size (8)));
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half4 hv0, hv1;
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short4 sv0;
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// CHECK-LABEL: testFP16Vec0
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// CHECK: %[[V0:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
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// CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>
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// CHECK: %[[V1:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
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// CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>
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// CHECK: %[[ADD:.*]] = fadd <4 x float> %[[CONV]], %[[CONV1]]
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// CHECK: %[[CONV2:.*]] = fptrunc <4 x float> %[[ADD]] to <4 x half>
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// CHECK: store <4 x half> %[[CONV2]], <4 x half>* @hv0, align 8
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// CHECK: %[[V2:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
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// CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>
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// CHECK: %[[V3:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
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// CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>
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// CHECK: %[[SUB:.*]] = fsub <4 x float> %[[CONV3]], %[[CONV4]]
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// CHECK: %[[CONV5:.*]] = fptrunc <4 x float> %[[SUB]] to <4 x half>
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// CHECK: store <4 x half> %[[CONV5]], <4 x half>* @hv0, align 8
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// CHECK: %[[V4:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
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// CHECK: %[[CONV6:.*]] = fpext <4 x half> %[[V4]] to <4 x float>
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// CHECK: %[[V5:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
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// CHECK: %[[CONV7:.*]] = fpext <4 x half> %[[V5]] to <4 x float>
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// CHECK: %[[MUL:.*]] = fmul <4 x float> %[[CONV6]], %[[CONV7]]
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// CHECK: %[[CONV8:.*]] = fptrunc <4 x float> %[[MUL]] to <4 x half>
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// CHECK: store <4 x half> %[[CONV8]], <4 x half>* @hv0, align 8
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// CHECK: %[[V6:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
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// CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V6]] to <4 x float>
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// CHECK: %[[V7:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
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// CHECK: %[[CONV10:.*]] = fpext <4 x half> %[[V7]] to <4 x float>
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// CHECK: %[[DIV:.*]] = fdiv <4 x float> %[[CONV9]], %[[CONV10]]
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// CHECK: %[[CONV11:.*]] = fptrunc <4 x float> %[[DIV]] to <4 x half>
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// CHECK: store <4 x half> %[[CONV11]], <4 x half>* @hv0, align 8
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void testFP16Vec0() {
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hv0 = hv0 + hv1;
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hv0 = hv0 - hv1;
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hv0 = hv0 * hv1;
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hv0 = hv0 / hv1;
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}
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// CHECK-LABEL: testFP16Vec1
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// CHECK: %[[V0:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
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// CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>
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// CHECK: %[[V1:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
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// CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>
|
||||
// CHECK: %[[ADD:.*]] = fadd <4 x float> %[[CONV1]], %[[CONV]]
|
||||
// CHECK: %[[CONV2:.*]] = fptrunc <4 x float> %[[ADD]] to <4 x half>
|
||||
// CHECK: store <4 x half> %[[CONV2]], <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[V2:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>
|
||||
// CHECK: %[[V3:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>
|
||||
// CHECK: %[[SUB:.*]] = fsub <4 x float> %[[CONV4]], %[[CONV3]]
|
||||
// CHECK: %[[CONV5:.*]] = fptrunc <4 x float> %[[SUB]] to <4 x half>
|
||||
// CHECK: store <4 x half> %[[CONV5]], <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[V4:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV6:.*]] = fpext <4 x half> %[[V4]] to <4 x float>
|
||||
// CHECK: %[[V5:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV7:.*]] = fpext <4 x half> %[[V5]] to <4 x float>
|
||||
// CHECK: %[[MUL:.*]] = fmul <4 x float> %[[CONV7]], %[[CONV6]]
|
||||
// CHECK: %[[CONV8:.*]] = fptrunc <4 x float> %[[MUL]] to <4 x half>
|
||||
// CHECK: store <4 x half> %[[CONV8]], <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[V6:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V6]] to <4 x float>
|
||||
// CHECK: %[[V7:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV10:.*]] = fpext <4 x half> %[[V7]] to <4 x float>
|
||||
// CHECK: %[[DIV:.*]] = fdiv <4 x float> %[[CONV10]], %[[CONV9]]
|
||||
// CHECK: %[[CONV11:.*]] = fptrunc <4 x float> %[[DIV]] to <4 x half>
|
||||
// CHECK: store <4 x half> %[[CONV11]], <4 x half>* @hv0, align 8
|
||||
|
||||
void testFP16Vec1() {
|
||||
hv0 += hv1;
|
||||
hv0 -= hv1;
|
||||
hv0 *= hv1;
|
||||
hv0 /= hv1;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: testFP16Vec2
|
||||
// CHECK: %[[CADDR:.*]] = alloca i32, align 4
|
||||
// CHECK: store i32 %[[C:.*]], i32* %[[CADDR]], align 4
|
||||
// CHECK: %[[V0:.*]] = load i32, i32* %[[CADDR]], align 4
|
||||
// CHECK: %[[TOBOOL:.*]] = icmp ne i32 %[[V0]], 0
|
||||
// CHECK: br i1 %[[TOBOOL]], label %{{.*}}, label %{{.*}}
|
||||
//
|
||||
// CHECK: %[[V1:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: br label %{{.*}}
|
||||
//
|
||||
// CHECK: %[[V2:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: br label %{{.*}}
|
||||
//
|
||||
// CHECK: %[[COND:.*]] = phi <4 x half> [ %[[V1]], %{{.*}} ], [ %[[V2]], %{{.*}} ]
|
||||
// CHECK: store <4 x half> %[[COND]], <4 x half>* @hv0, align 8
|
||||
|
||||
void testFP16Vec2(int c) {
|
||||
hv0 = c ? hv0 : hv1;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: testFP16Vec3
|
||||
// CHECK: %[[V0:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV:.*]] = fpext <4 x half> %[[V0]] to <4 x float>
|
||||
// CHECK: %[[V1:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV1:.*]] = fpext <4 x half> %[[V1]] to <4 x float>
|
||||
// CHECK: %[[CMP:.*]] = fcmp oeq <4 x float> %[[CONV]], %[[CONV1]]
|
||||
// CHECK: %[[SEXT:.*]] = sext <4 x i1> %[[CMP]] to <4 x i32>
|
||||
// CHECK: %[[CONV2:.*]] = trunc <4 x i32> %[[SEXT]] to <4 x i16>
|
||||
// CHECK: store <4 x i16> %[[CONV2]], <4 x i16>* @sv0, align 8
|
||||
// CHECK: %[[V2:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV3:.*]] = fpext <4 x half> %[[V2]] to <4 x float>
|
||||
// CHECK: %[[V3:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV4:.*]] = fpext <4 x half> %[[V3]] to <4 x float>
|
||||
// CHECK: %[[CMP5:.*]] = fcmp une <4 x float> %[[CONV3]], %[[CONV4]]
|
||||
// CHECK: %[[SEXT6:.*]] = sext <4 x i1> %[[CMP5]] to <4 x i32>
|
||||
// CHECK: %[[CONV7:.*]] = trunc <4 x i32> %[[SEXT6]] to <4 x i16>
|
||||
// CHECK: store <4 x i16> %[[CONV7]], <4 x i16>* @sv0, align 8
|
||||
// CHECK: %[[V4:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV8:.*]] = fpext <4 x half> %[[V4]] to <4 x float>
|
||||
// CHECK: %[[V5:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV9:.*]] = fpext <4 x half> %[[V5]] to <4 x float>
|
||||
// CHECK: %[[CMP10:.*]] = fcmp olt <4 x float> %[[CONV8]], %[[CONV9]]
|
||||
// CHECK: %[[SEXT11:.*]] = sext <4 x i1> %[[CMP10]] to <4 x i32>
|
||||
// CHECK: %[[CONV12:.*]] = trunc <4 x i32> %[[SEXT11]] to <4 x i16>
|
||||
// CHECK: store <4 x i16> %[[CONV12]], <4 x i16>* @sv0, align 8
|
||||
// CHECK: %[[V6:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV13:.*]] = fpext <4 x half> %[[V6]] to <4 x float>
|
||||
// CHECK: %[[V7:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV14:.*]] = fpext <4 x half> %[[V7]] to <4 x float>
|
||||
// CHECK: %[[CMP15:.*]] = fcmp ogt <4 x float> %[[CONV13]], %[[CONV14]]
|
||||
// CHECK: %[[SEXT16:.*]] = sext <4 x i1> %[[CMP15]] to <4 x i32>
|
||||
// CHECK: %[[CONV17:.*]] = trunc <4 x i32> %[[SEXT16]] to <4 x i16>
|
||||
// CHECK: store <4 x i16> %[[CONV17]], <4 x i16>* @sv0, align 8
|
||||
// CHECK: %[[V8:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV18:.*]] = fpext <4 x half> %[[V8]] to <4 x float>
|
||||
// CHECK: %[[V9:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV19:.*]] = fpext <4 x half> %[[V9]] to <4 x float>
|
||||
// CHECK: %[[CMP20:.*]] = fcmp ole <4 x float> %[[CONV18]], %[[CONV19]]
|
||||
// CHECK: %[[SEXT21:.*]] = sext <4 x i1> %[[CMP20]] to <4 x i32>
|
||||
// CHECK: %[[CONV22:.*]] = trunc <4 x i32> %[[SEXT21]] to <4 x i16>
|
||||
// CHECK: store <4 x i16> %[[CONV22]], <4 x i16>* @sv0, align 8
|
||||
// CHECK: %[[V10:.*]] = load <4 x half>, <4 x half>* @hv0, align 8
|
||||
// CHECK: %[[CONV23:.*]] = fpext <4 x half> %[[V10]] to <4 x float>
|
||||
// CHECK: %[[V11:.*]] = load <4 x half>, <4 x half>* @hv1, align 8
|
||||
// CHECK: %[[CONV24:.*]] = fpext <4 x half> %[[V11]] to <4 x float>
|
||||
// CHECK: %[[CMP25:.*]] = fcmp oge <4 x float> %[[CONV23]], %[[CONV24]]
|
||||
// CHECK: %[[SEXT26:.*]] = sext <4 x i1> %[[CMP25]] to <4 x i32>
|
||||
// CHECK: %[[CONV27:.*]] = trunc <4 x i32> %[[SEXT26]] to <4 x i16>
|
||||
// CHECK: store <4 x i16> %[[CONV27]], <4 x i16>* @sv0, align 8
|
||||
|
||||
void testFP16Vec3() {
|
||||
sv0 = hv0 == hv1;
|
||||
sv0 = hv0 != hv1;
|
||||
sv0 = hv0 < hv1;
|
||||
sv0 = hv0 > hv1;
|
||||
sv0 = hv0 <= hv1;
|
||||
sv0 = hv0 >= hv1;
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
// RUN: %clang_cc1 -fsyntax-only -verify %s
|
||||
|
||||
typedef __fp16 half4 __attribute__ ((vector_size (8)));
|
||||
typedef float float4 __attribute__ ((vector_size (16)));
|
||||
typedef short short4 __attribute__ ((vector_size (8)));
|
||||
typedef int int4 __attribute__ ((vector_size (16)));
|
||||
|
||||
half4 hv0, hv1;
|
||||
float4 fv0, fv1;
|
||||
short4 sv0;
|
||||
int4 iv0;
|
||||
|
||||
void testFP16Vec(int c) {
|
||||
hv0 = hv0 + hv1;
|
||||
hv0 = hv0 - hv1;
|
||||
hv0 = hv0 * hv1;
|
||||
hv0 = hv0 / hv1;
|
||||
hv0 = c ? hv0 : hv1;
|
||||
hv0 += hv1;
|
||||
hv0 -= hv1;
|
||||
hv0 *= hv1;
|
||||
hv0 /= hv1;
|
||||
sv0 = hv0 == hv1;
|
||||
sv0 = hv0 != hv1;
|
||||
sv0 = hv0 < hv1;
|
||||
sv0 = hv0 > hv1;
|
||||
sv0 = hv0 <= hv1;
|
||||
sv0 = hv0 >= hv1;
|
||||
sv0 = hv0 || hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
|
||||
sv0 = hv0 && hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
|
||||
|
||||
// Implicit conversion between half vectors and float vectors are not allowed.
|
||||
hv0 = fv0; // expected-error{{assigning to}}
|
||||
fv0 = hv0; // expected-error{{assigning to}}
|
||||
hv0 = (half4)fv0; // expected-error{{invalid conversion between}}
|
||||
fv0 = (float4)hv0; // expected-error{{invalid conversion between}}
|
||||
hv0 = fv0 + fv1; // expected-error{{assigning to}}
|
||||
fv0 = hv0 + hv1; // expected-error{{assigning to}}
|
||||
hv0 = hv0 + fv1; // expected-error{{cannot convert between vector}}
|
||||
hv0 = c ? hv0 : fv1; // expected-error{{cannot convert between vector}}
|
||||
sv0 = hv0 == fv1; // expected-error{{cannot convert between vector}}
|
||||
sv0 = hv0 < fv1; // expected-error{{cannot convert between vector}}
|
||||
sv0 = hv0 || fv1; // expected-error{{cannot convert between vector}} expected-error{{invalid operands to binary expression}}
|
||||
iv0 = hv0 == hv1; // expected-error{{assigning to}}
|
||||
|
||||
// FIXME: clang currently disallows using these operators on vectors, which is
|
||||
// allowed by gcc.
|
||||
sv0 = !hv0; // expected-error{{invalid argument type}}
|
||||
hv0++; // expected-error{{cannot increment value of type}}
|
||||
++hv0; // expected-error{{cannot increment value of type}}
|
||||
}
|
||||
Loading…
Reference in New Issue