mirror of https://github.com/microsoft/clang.git
[MS] Re-add support for the ARM interlocked bittest intrinscs
Adds support for these intrinsics, which are ARM and ARM64 only: _interlockedbittestandreset_acq _interlockedbittestandreset_rel _interlockedbittestandreset_nf _interlockedbittestandset_acq _interlockedbittestandset_rel _interlockedbittestandset_nf Refactor the bittest intrinsic handling to decompose each intrinsic into its action, its width, and its atomicity. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@334239 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reid Kleckner
parent
2dbbac4ddd
commit
c1c07cca8c
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@ -791,10 +791,16 @@ LANGBUILTIN(_InterlockedOr, "NiNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_InterlockedXor8, "ccD*c", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_InterlockedXor16, "ssD*s", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_InterlockedXor, "NiNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandreset, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandreset64, "UcWiD*Wi", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandset, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandset64, "UcWiD*Wi", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandreset, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandreset64, "UcWiD*Wi", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandreset_acq, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandreset_nf, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandreset_rel, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandset, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandset64, "UcWiD*Wi", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandset_acq, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandset_nf, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(_interlockedbittestandset_rel, "UcNiD*Ni", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(__noop, "i.", "n", ALL_MS_LANGUAGES)
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LANGBUILTIN(__popcnt16, "UsUs", "nc", ALL_MS_LANGUAGES)
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LANGBUILTIN(__popcnt, "UiUi", "nc", ALL_MS_LANGUAGES)
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@ -8154,6 +8154,8 @@ def err_x86_builtin_invalid_rounding : Error<
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"invalid rounding argument">;
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def err_x86_builtin_invalid_scale : Error<
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"scale argument must be 1, 2, 4, or 8">;
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def err_builtin_target_unsupported : Error<
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"builtin is not supported on this target">;
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def err_builtin_longjmp_unsupported : Error<
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"__builtin_longjmp is not supported for the current target">;
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@ -484,58 +484,99 @@ CodeGenFunction::emitBuiltinObjectSize(const Expr *E, unsigned Type,
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return Builder.CreateCall(F, {Ptr, Min, NullIsUnknown});
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}
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// Get properties of an X86 BT* assembly instruction. The first returned value
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// is the action character code, which can be for complement, reset, or set. The
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// second is the size suffix which our assembler needs. The last is whether to
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// add the lock prefix.
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static std::tuple<char, char, bool>
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getBitTestActionSizeAndLocking(unsigned BuiltinID) {
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switch (BuiltinID) {
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case Builtin::BI_bittest:
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return std::make_tuple('\0', 'l', false);
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case Builtin::BI_bittestandcomplement:
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return std::make_tuple('c', 'l', false);
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case Builtin::BI_bittestandreset:
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return std::make_tuple('r', 'l', false);
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case Builtin::BI_bittestandset:
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return std::make_tuple('s', 'l', false);
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case Builtin::BI_interlockedbittestandreset:
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return std::make_tuple('r', 'l', /*Locked=*/true);
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case Builtin::BI_interlockedbittestandset:
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return std::make_tuple('s', 'l', /*Locked=*/true);
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namespace {
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/// A struct to generically desribe a bit test intrinsic.
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struct BitTest {
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enum ActionKind : uint8_t { TestOnly, Complement, Reset, Set };
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enum InterlockingKind : uint8_t {
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Unlocked,
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Sequential,
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Acquire,
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Release,
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NoFence
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};
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ActionKind Action;
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InterlockingKind Interlocking;
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bool Is64Bit;
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static BitTest decodeBitTestBuiltin(unsigned BuiltinID);
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};
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} // namespace
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BitTest BitTest::decodeBitTestBuiltin(unsigned BuiltinID) {
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switch (BuiltinID) {
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// Main portable variants.
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case Builtin::BI_bittest:
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return {TestOnly, Unlocked, false};
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case Builtin::BI_bittestandcomplement:
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return {Complement, Unlocked, false};
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case Builtin::BI_bittestandreset:
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return {Reset, Unlocked, false};
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case Builtin::BI_bittestandset:
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return {Set, Unlocked, false};
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case Builtin::BI_interlockedbittestandreset:
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return {Reset, Sequential, false};
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case Builtin::BI_interlockedbittestandset:
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return {Set, Sequential, false};
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// X86-specific 64-bit variants.
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case Builtin::BI_bittest64:
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return std::make_tuple('\0', 'q', false);
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return {TestOnly, Unlocked, true};
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case Builtin::BI_bittestandcomplement64:
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return std::make_tuple('c', 'q', false);
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return {Complement, Unlocked, true};
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case Builtin::BI_bittestandreset64:
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return std::make_tuple('r', 'q', false);
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return {Reset, Unlocked, true};
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case Builtin::BI_bittestandset64:
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return std::make_tuple('s', 'q', false);
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return {Set, Unlocked, true};
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case Builtin::BI_interlockedbittestandreset64:
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return std::make_tuple('r', 'q', /*Locked=*/true);
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return {Reset, Sequential, true};
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case Builtin::BI_interlockedbittestandset64:
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return std::make_tuple('s', 'q', /*Locked=*/true);
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return {Set, Sequential, true};
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// ARM/AArch64-specific ordering variants.
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case Builtin::BI_interlockedbittestandset_acq:
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return {Set, Acquire, false};
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case Builtin::BI_interlockedbittestandset_rel:
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return {Set, Release, false};
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case Builtin::BI_interlockedbittestandset_nf:
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return {Set, NoFence, false};
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case Builtin::BI_interlockedbittestandreset_acq:
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return {Reset, Acquire, false};
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case Builtin::BI_interlockedbittestandreset_rel:
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return {Reset, Release, false};
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case Builtin::BI_interlockedbittestandreset_nf:
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return {Reset, NoFence, false};
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}
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llvm_unreachable("expected only bittest builtins");
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llvm_unreachable("expected only bittest intrinsics");
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}
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static RValue EmitX86BitTestIntrinsic(CodeGenFunction &CGF, unsigned BuiltinID,
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const CallExpr *E, Value *BitBase,
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Value *BitPos) {
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char Action, Size;
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bool Locked;
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std::tie(Action, Size, Locked) = getBitTestActionSizeAndLocking(BuiltinID);
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static char bitActionToX86BTCode(BitTest::ActionKind A) {
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switch (A) {
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case BitTest::TestOnly: return '\0';
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case BitTest::Complement: return 'c';
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case BitTest::Reset: return 'r';
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case BitTest::Set: return 's';
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}
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llvm_unreachable("invalid action");
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}
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static llvm::Value *EmitX86BitTestIntrinsic(CodeGenFunction &CGF,
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BitTest BT,
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const CallExpr *E, Value *BitBase,
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Value *BitPos) {
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char Action = bitActionToX86BTCode(BT.Action);
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char SizeSuffix = BT.Is64Bit ? 'q' : 'l';
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// Build the assembly.
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SmallString<64> Asm;
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raw_svector_ostream AsmOS(Asm);
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if (Locked)
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if (BT.Interlocking != BitTest::Unlocked)
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AsmOS << "lock ";
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AsmOS << "bt";
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if (Action)
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AsmOS << Action;
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AsmOS << Size << " $2, ($1)\n\tsetc ${0:b}";
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AsmOS << SizeSuffix << " $2, ($1)\n\tsetc ${0:b}";
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// Build the constraints. FIXME: We should support immediates when possible.
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std::string Constraints = "=r,r,r,~{cc},~{flags},~{fpsr}";
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@ -548,24 +589,38 @@ static RValue EmitX86BitTestIntrinsic(CodeGenFunction &CGF, unsigned BuiltinID,
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llvm::InlineAsm *IA =
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llvm::InlineAsm::get(FTy, Asm, Constraints, /*SideEffects=*/true);
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CallSite CS = CGF.Builder.CreateCall(IA, {BitBase, BitPos});
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return RValue::get(CS.getInstruction());
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return CGF.Builder.CreateCall(IA, {BitBase, BitPos});
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}
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static llvm::AtomicOrdering
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getBitTestAtomicOrdering(BitTest::InterlockingKind I) {
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switch (I) {
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case BitTest::Unlocked: return llvm::AtomicOrdering::NotAtomic;
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case BitTest::Sequential: return llvm::AtomicOrdering::SequentiallyConsistent;
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case BitTest::Acquire: return llvm::AtomicOrdering::Acquire;
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case BitTest::Release: return llvm::AtomicOrdering::Release;
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case BitTest::NoFence: return llvm::AtomicOrdering::Monotonic;
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}
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llvm_unreachable("invalid interlocking");
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}
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/// Emit a _bittest* intrinsic. These intrinsics take a pointer to an array of
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/// bits and a bit position and read and optionally modify the bit at that
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/// position. The position index can be arbitrarily large, i.e. it can be larger
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/// than 31 or 63, so we need an indexed load in the general case.
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static RValue EmitBitTestIntrinsic(CodeGenFunction &CGF, unsigned BuiltinID,
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const CallExpr *E) {
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static llvm::Value *EmitBitTestIntrinsic(CodeGenFunction &CGF,
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unsigned BuiltinID,
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const CallExpr *E) {
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Value *BitBase = CGF.EmitScalarExpr(E->getArg(0));
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Value *BitPos = CGF.EmitScalarExpr(E->getArg(1));
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BitTest BT = BitTest::decodeBitTestBuiltin(BuiltinID);
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// X86 has special BT, BTC, BTR, and BTS instructions that handle the array
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// indexing operation internally. Use them if possible.
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llvm::Triple::ArchType Arch = CGF.getTarget().getTriple().getArch();
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if (Arch == llvm::Triple::x86 || Arch == llvm::Triple::x86_64)
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return EmitX86BitTestIntrinsic(CGF, BuiltinID, E, BitBase, BitPos);
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return EmitX86BitTestIntrinsic(CGF, BT, E, BitBase, BitPos);
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// Otherwise, use generic code to load one byte and test the bit. Use all but
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// the bottom three bits as the array index, and the bottom three bits to form
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@ -583,54 +638,42 @@ static RValue EmitBitTestIntrinsic(CodeGenFunction &CGF, unsigned BuiltinID,
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// The updating instructions will need a mask.
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Value *Mask = nullptr;
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if (BuiltinID != Builtin::BI_bittest && BuiltinID != Builtin::BI_bittest64) {
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if (BT.Action != BitTest::TestOnly) {
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Mask = CGF.Builder.CreateShl(llvm::ConstantInt::get(CGF.Int8Ty, 1), PosLow,
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"bittest.mask");
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}
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// Emit a combined atomicrmw load/store operation for the interlocked
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// intrinsics.
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Value *OldByte = nullptr;
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switch (BuiltinID) {
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case Builtin::BI_interlockedbittestandreset:
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case Builtin::BI_interlockedbittestandreset64:
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OldByte = CGF.Builder.CreateAtomicRMW(
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AtomicRMWInst::And, ByteAddr.getPointer(), CGF.Builder.CreateNot(Mask),
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llvm::AtomicOrdering::SequentiallyConsistent);
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break;
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case Builtin::BI_interlockedbittestandset:
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case Builtin::BI_interlockedbittestandset64:
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OldByte = CGF.Builder.CreateAtomicRMW(
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AtomicRMWInst::Or, ByteAddr.getPointer(), Mask,
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llvm::AtomicOrdering::SequentiallyConsistent);
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break;
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default:
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break;
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}
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// Check the action and ordering of the interlocked intrinsics.
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llvm::AtomicOrdering Ordering = getBitTestAtomicOrdering(BT.Interlocking);
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// Emit a plain load for the non-interlocked intrinsics.
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if (!OldByte) {
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Value *OldByte = nullptr;
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if (Ordering != llvm::AtomicOrdering::NotAtomic) {
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// Emit a combined atomicrmw load/store operation for the interlocked
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// intrinsics.
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llvm::AtomicRMWInst::BinOp RMWOp = llvm::AtomicRMWInst::Or;
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if (BT.Action == BitTest::Reset) {
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Mask = CGF.Builder.CreateNot(Mask);
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RMWOp = llvm::AtomicRMWInst::And;
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}
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OldByte = CGF.Builder.CreateAtomicRMW(RMWOp, ByteAddr.getPointer(), Mask,
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Ordering);
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} else {
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// Emit a plain load for the non-interlocked intrinsics.
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OldByte = CGF.Builder.CreateLoad(ByteAddr, "bittest.byte");
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Value *NewByte = nullptr;
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switch (BuiltinID) {
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case Builtin::BI_bittest:
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case Builtin::BI_bittest64:
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switch (BT.Action) {
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case BitTest::TestOnly:
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// Don't store anything.
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break;
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case Builtin::BI_bittestandcomplement:
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case Builtin::BI_bittestandcomplement64:
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case BitTest::Complement:
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NewByte = CGF.Builder.CreateXor(OldByte, Mask);
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break;
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case Builtin::BI_bittestandreset:
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case Builtin::BI_bittestandreset64:
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case BitTest::Reset:
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NewByte = CGF.Builder.CreateAnd(OldByte, CGF.Builder.CreateNot(Mask));
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break;
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case Builtin::BI_bittestandset:
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case Builtin::BI_bittestandset64:
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case BitTest::Set:
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NewByte = CGF.Builder.CreateOr(OldByte, Mask);
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break;
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default:
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llvm_unreachable("non bittest family builtin");
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}
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if (NewByte)
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CGF.Builder.CreateStore(NewByte, ByteAddr);
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@ -639,8 +682,8 @@ static RValue EmitBitTestIntrinsic(CodeGenFunction &CGF, unsigned BuiltinID,
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// However we loaded the old byte, either by plain load or atomicrmw, shift
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// the bit into the low position and mask it to 0 or 1.
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Value *ShiftedByte = CGF.Builder.CreateLShr(OldByte, PosLow, "bittest.shr");
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return RValue::get(CGF.Builder.CreateAnd(
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ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res"));
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return CGF.Builder.CreateAnd(
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ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
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}
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namespace {
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@ -2992,7 +3035,13 @@ RValue CodeGenFunction::EmitBuiltinExpr(const FunctionDecl *FD,
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case Builtin::BI_interlockedbittestandreset64:
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case Builtin::BI_interlockedbittestandset64:
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case Builtin::BI_interlockedbittestandset:
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return EmitBitTestIntrinsic(*this, BuiltinID, E);
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case Builtin::BI_interlockedbittestandset_acq:
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case Builtin::BI_interlockedbittestandset_rel:
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case Builtin::BI_interlockedbittestandset_nf:
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case Builtin::BI_interlockedbittestandreset_acq:
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case Builtin::BI_interlockedbittestandreset_rel:
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case Builtin::BI_interlockedbittestandreset_nf:
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return RValue::get(EmitBitTestIntrinsic(*this, BuiltinID, E));
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case Builtin::BI__exception_code:
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case Builtin::BI_exception_code:
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@ -521,6 +521,23 @@ _InterlockedAnd64_rel(__int64 volatile *_Value, __int64 _Mask) {
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}
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#endif
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/*----------------------------------------------------------------------------*\
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|* Bit Counting and Testing
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\*----------------------------------------------------------------------------*/
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#if defined(__arm__) || defined(__aarch64__)
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unsigned char _interlockedbittestandset_acq(long volatile *_BitBase,
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long _BitPos);
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unsigned char _interlockedbittestandset_nf(long volatile *_BitBase,
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long _BitPos);
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unsigned char _interlockedbittestandset_rel(long volatile *_BitBase,
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long _BitPos);
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unsigned char _interlockedbittestandreset_acq(long volatile *_BitBase,
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long _BitPos);
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unsigned char _interlockedbittestandreset_nf(long volatile *_BitBase,
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long _BitPos);
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unsigned char _interlockedbittestandreset_rel(long volatile *_BitBase,
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long _BitPos);
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#endif
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/*----------------------------------------------------------------------------*\
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|* Interlocked Or
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\*----------------------------------------------------------------------------*/
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#if defined(__arm__) || defined(__aarch64__)
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@ -851,6 +851,20 @@ static bool SemaOpenCLBuiltinToAddr(Sema &S, unsigned BuiltinID,
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return false;
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}
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// Emit an error and return true if the current architecture is not in the list
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// of supported architectures.
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static bool
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CheckBuiltinTargetSupport(Sema &S, unsigned BuiltinID, CallExpr *TheCall,
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ArrayRef<llvm::Triple::ArchType> SupportedArchs) {
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llvm::Triple::ArchType CurArch =
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S.getASTContext().getTargetInfo().getTriple().getArch();
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if (llvm::is_contained(SupportedArchs, CurArch))
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return false;
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S.Diag(TheCall->getLocStart(), diag::err_builtin_target_unsupported)
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<< TheCall->getSourceRange();
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return true;
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}
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ExprResult
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Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
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CallExpr *TheCall) {
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@ -901,6 +915,33 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
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}
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break;
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}
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// The acquire, release, and no fence variants are ARM and AArch64 only.
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case Builtin::BI_interlockedbittestandset_acq:
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case Builtin::BI_interlockedbittestandset_rel:
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case Builtin::BI_interlockedbittestandset_nf:
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case Builtin::BI_interlockedbittestandreset_acq:
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case Builtin::BI_interlockedbittestandreset_rel:
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case Builtin::BI_interlockedbittestandreset_nf:
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if (CheckBuiltinTargetSupport(
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||||
*this, BuiltinID, TheCall,
|
||||
{llvm::Triple::arm, llvm::Triple::thumb, llvm::Triple::aarch64}))
|
||||
return ExprError();
|
||||
break;
|
||||
|
||||
// The 64-bit bittest variants are x64, ARM, and AArch64 only.
|
||||
case Builtin::BI_bittest64:
|
||||
case Builtin::BI_bittestandcomplement64:
|
||||
case Builtin::BI_bittestandreset64:
|
||||
case Builtin::BI_bittestandset64:
|
||||
case Builtin::BI_interlockedbittestandreset64:
|
||||
case Builtin::BI_interlockedbittestandset64:
|
||||
if (CheckBuiltinTargetSupport(*this, BuiltinID, TheCall,
|
||||
{llvm::Triple::x86_64, llvm::Triple::arm,
|
||||
llvm::Triple::thumb, llvm::Triple::aarch64}))
|
||||
return ExprError();
|
||||
break;
|
||||
|
||||
case Builtin::BI__builtin_isgreater:
|
||||
case Builtin::BI__builtin_isgreaterequal:
|
||||
case Builtin::BI__builtin_isless:
|
||||
|
|
|
|||
|
|
@ -10,7 +10,9 @@ void test32(long *base, long idx) {
|
|||
sink = _bittestandset(base, idx);
|
||||
sink = _interlockedbittestandreset(base, idx);
|
||||
sink = _interlockedbittestandset(base, idx);
|
||||
sink = _interlockedbittestandset(base, idx);
|
||||
}
|
||||
|
||||
void test64(__int64 *base, __int64 idx) {
|
||||
sink = _bittest64(base, idx);
|
||||
sink = _bittestandcomplement64(base, idx);
|
||||
|
|
@ -20,6 +22,17 @@ void test64(__int64 *base, __int64 idx) {
|
|||
sink = _interlockedbittestandset64(base, idx);
|
||||
}
|
||||
|
||||
#if defined(_M_ARM) || defined(_M_ARM64)
|
||||
void test_arm(long *base, long idx) {
|
||||
sink = _interlockedbittestandreset_acq(base, idx);
|
||||
sink = _interlockedbittestandreset_rel(base, idx);
|
||||
sink = _interlockedbittestandreset_nf(base, idx);
|
||||
sink = _interlockedbittestandset_acq(base, idx);
|
||||
sink = _interlockedbittestandset_rel(base, idx);
|
||||
sink = _interlockedbittestandset_nf(base, idx);
|
||||
}
|
||||
#endif
|
||||
|
||||
// X64-LABEL: define dso_local void @test32(i32* %base, i32 %idx)
|
||||
// X64: call i8 asm sideeffect "btl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{{.*}}"(i32* %{{.*}}, i32 {{.*}})
|
||||
// X64: call i8 asm sideeffect "btcl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{{.*}}"(i32* %{{.*}}, i32 {{.*}})
|
||||
|
|
@ -110,15 +123,13 @@ void test64(__int64 *base, __int64 idx) {
|
|||
// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
|
||||
// ARM: store volatile i8 %[[RES]], i8* @sink, align 1
|
||||
|
||||
// ARM-LABEL: define dso_local {{.*}}void @test64(i64* %base, i64 %idx)
|
||||
// ARM: %[[IDXHI:[^ ]*]] = ashr i64 %{{.*}}, 3
|
||||
// ARM: %[[BASE:[^ ]*]] = bitcast i64* %{{.*}} to i8*
|
||||
// ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i64 %[[IDXHI]]
|
||||
// ARM: %[[IDX8:[^ ]*]] = trunc i64 %{{.*}} to i8
|
||||
// ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
|
||||
// ARM: %[[BYTE:[^ ]*]] = load i8, i8* %[[BYTEADDR]], align 1
|
||||
// ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
|
||||
// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
|
||||
// ARM: store volatile i8 %[[RES]], i8* @sink, align 1
|
||||
|
||||
// ... the rest is the same, but with i64 instead of i32.
|
||||
// Just look for the atomicrmw instructions.
|
||||
|
||||
// ARM-LABEL: define dso_local {{.*}}void @test_arm(i32* %base, i32 %idx)
|
||||
// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} acquire
|
||||
// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} release
|
||||
// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} monotonic
|
||||
// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} acquire
|
||||
// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} release
|
||||
// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} monotonic
|
||||
|
|
|
|||
|
|
@ -0,0 +1,84 @@
|
|||
// RUN: %clang_cc1 -ffreestanding -fms-compatibility -fms-compatibility-version=19 -verify %s -triple i686-windows-msvc -fms-extensions -DTEST_X86
|
||||
// RUN: %clang_cc1 -ffreestanding -fms-compatibility -fms-compatibility-version=19 -verify %s -triple x86_64-windows-msvc -fms-extensions -DTEST_X64
|
||||
// RUN: %clang_cc1 -ffreestanding -fms-compatibility -fms-compatibility-version=19 -verify %s -triple arm-windows-msvc -fms-extensions -DTEST_ARM
|
||||
// RUN: %clang_cc1 -ffreestanding -fms-compatibility -fms-compatibility-version=19 -verify %s -triple thumbv7-windows-msvc -fms-extensions -DTEST_ARM
|
||||
// RUN: %clang_cc1 -ffreestanding -fms-compatibility -fms-compatibility-version=19 -verify %s -triple aarch64-windows-msvc -fms-extensions -DTEST_ARM
|
||||
|
||||
#include <intrin.h>
|
||||
extern unsigned char sink;
|
||||
|
||||
#ifdef TEST_X86
|
||||
void x86(long *bits, __int64 *bits64, long bitidx) {
|
||||
sink = _bittest(bits, bitidx);
|
||||
sink = _bittestandcomplement(bits, bitidx);
|
||||
sink = _bittestandreset(bits, bitidx);
|
||||
sink = _bittestandset(bits, bitidx);
|
||||
sink = _interlockedbittestandreset(bits, bitidx);
|
||||
sink = _interlockedbittestandset(bits, bitidx);
|
||||
|
||||
sink = _bittest64(bits64, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _bittestandcomplement64(bits64, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _bittestandreset64(bits64, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _bittestandset64(bits64, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandreset64(bits64, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandset64(bits64, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
|
||||
sink = _interlockedbittestandreset_acq(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandreset_rel(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandreset_nf(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandset_acq(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandset_rel(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandset_nf(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef TEST_X64
|
||||
void x64(long *bits, __int64 *bits64, long bitidx) {
|
||||
sink = _bittest(bits, bitidx);
|
||||
sink = _bittestandcomplement(bits, bitidx);
|
||||
sink = _bittestandreset(bits, bitidx);
|
||||
sink = _bittestandset(bits, bitidx);
|
||||
sink = _interlockedbittestandreset(bits, bitidx);
|
||||
sink = _interlockedbittestandset(bits, bitidx);
|
||||
|
||||
sink = _bittest64(bits64, bitidx);
|
||||
sink = _bittestandcomplement64(bits64, bitidx);
|
||||
sink = _bittestandreset64(bits64, bitidx);
|
||||
sink = _bittestandset64(bits64, bitidx);
|
||||
sink = _interlockedbittestandreset64(bits64, bitidx);
|
||||
sink = _interlockedbittestandset64(bits64, bitidx);
|
||||
|
||||
sink = _interlockedbittestandreset_acq(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandreset_rel(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandreset_nf(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandset_acq(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandset_rel(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
sink = _interlockedbittestandset_nf(bits, bitidx); // expected-error {{builtin is not supported on this target}}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef TEST_ARM
|
||||
// expected-no-diagnostics
|
||||
void arm(long *bits, __int64 *bits64, long bitidx) {
|
||||
sink = _bittest(bits, bitidx);
|
||||
sink = _bittestandcomplement(bits, bitidx);
|
||||
sink = _bittestandreset(bits, bitidx);
|
||||
sink = _bittestandset(bits, bitidx);
|
||||
sink = _interlockedbittestandreset(bits, bitidx);
|
||||
sink = _interlockedbittestandset(bits, bitidx);
|
||||
|
||||
sink = _bittest64(bits64, bitidx);
|
||||
sink = _bittestandcomplement64(bits64, bitidx);
|
||||
sink = _bittestandreset64(bits64, bitidx);
|
||||
sink = _bittestandset64(bits64, bitidx);
|
||||
sink = _interlockedbittestandreset64(bits64, bitidx);
|
||||
sink = _interlockedbittestandset64(bits64, bitidx);
|
||||
|
||||
sink = _interlockedbittestandreset_acq(bits, bitidx);
|
||||
sink = _interlockedbittestandreset_rel(bits, bitidx);
|
||||
sink = _interlockedbittestandreset_nf(bits, bitidx);
|
||||
sink = _interlockedbittestandset_acq(bits, bitidx);
|
||||
sink = _interlockedbittestandset_rel(bits, bitidx);
|
||||
sink = _interlockedbittestandset_nf(bits, bitidx);
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue