95 lines
1.5 KiB
Verilog
95 lines
1.5 KiB
Verilog
module top (
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input clk,
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input rst,
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input [7:0] sw,
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input ps2_clk,
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input ps2_data,
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output [15:0] ledr,
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output VGA_CLK,
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output VGA_HSYNC,
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output VGA_VSYNC,
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output VGA_BLANK_N,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output [7:0] seg0,
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output [7:0] seg1,
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output [7:0] seg2,
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output [7:0] seg3,
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output [7:0] seg4,
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output [7:0] seg5,
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output [7:0] seg6,
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output [7:0] seg7
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);
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led led1(
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.clk(clk),
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.rst(rst),
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.sw(sw),
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.ledr(ledr)
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);
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assign VGA_CLK = clk;
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wire [9:0] h_addr;
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wire [9:0] v_addr;
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wire [23:0] vga_data;
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vga_ctrl my_vga_ctrl(
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.pclk(clk),
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.reset(rst),
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.vga_data(vga_data),
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.h_addr(h_addr),
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.v_addr(v_addr),
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.hsync(VGA_HSYNC),
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.vsync(VGA_VSYNC),
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.valid(VGA_BLANK_N),
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.vga_r(VGA_R),
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.vga_g(VGA_G),
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.vga_b(VGA_B)
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);
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ps2_keyboard my_keyboard(
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.clk(clk),
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.resetn(~rst),
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.ps2_clk(ps2_clk),
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.ps2_data(ps2_data)
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);
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seg mu_seg(
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.clk(clk),
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.rst(rst),
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.o_seg0(seg0),
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.o_seg1(seg1),
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.o_seg2(seg2),
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.o_seg3(seg3),
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.o_seg4(seg4),
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.o_seg5(seg5),
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.o_seg6(seg6),
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.o_seg7(seg7)
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);
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vmem my_vmem(
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.h_addr(h_addr),
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.v_addr(v_addr[8:0]),
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.vga_data(vga_data)
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);
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endmodule
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module vmem (
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input [9:0] h_addr,
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input [8:0] v_addr,
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output [23:0] vga_data
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);
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reg [23:0] vga_mem [524287:0];
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initial begin
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$readmemh("resource/picture.hex", vga_mem);
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end
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assign vga_data = vga_mem[{h_addr, v_addr}];
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endmodule
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