39 lines
1.0 KiB
Verilog
39 lines
1.0 KiB
Verilog
module seg(
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input clk,
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input rst,
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output [7:0] o_seg0,
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output [7:0] o_seg1,
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output [7:0] o_seg2,
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output [7:0] o_seg3,
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output [7:0] o_seg4,
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output [7:0] o_seg5,
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output [7:0] o_seg6,
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output [7:0] o_seg7
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);
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parameter segs = {8'b01100001, 8'b11011010, 8'b11110010, 8'b01100110, 8'b10110110, 8'b10111110, 8'b11100000, 8'b11111110};
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parameter CLK_NUM = 500000;
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reg [31:0] count;
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reg [2:0] offset;
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always @(posedge clk) begin
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if(rst) begin count <= 0; offset <= 0; end
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else begin
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if(count == CLK_NUM) begin offset <= offset + 1; end
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count <= (count == CLK_NUM) ? 0 : count + 1;
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end
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end
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assign o_seg1 = ~(segs>> (((offset + 3'd0)&7) * 8));
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assign o_seg2 = ~(segs>> (((offset + 3'd1)&7) * 8));
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assign o_seg3 = ~(segs>> (((offset + 3'd2)&7) * 8));
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assign o_seg4 = ~(segs>> (((offset + 3'd3)&7) * 8));
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assign o_seg5 = ~(segs>> (((offset + 3'd4)&7) * 8));
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assign o_seg6 = ~(segs>> (((offset + 3'd5)&7) * 8));
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assign o_seg7 = ~(segs>> (((offset + 3'd6)&7) * 8));
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assign o_seg8 = ~(segs>> (((offset + 3'd7)&7) * 8));
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endmodule
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