37 lines
1.1 KiB
Verilog
37 lines
1.1 KiB
Verilog
module ps2_keyboard(clk,resetn,ps2_clk,ps2_data);
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input clk,resetn,ps2_clk,ps2_data;
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reg [9:0] buffer; // ps2_data bits
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reg [3:0] count; // count ps2_data bits
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reg [2:0] ps2_clk_sync;
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reg pre_clk;
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always @(posedge clk) begin
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ps2_clk_sync <= {ps2_clk_sync[1:0],ps2_clk};
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pre_clk <= clk;
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end
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wire sampling = ps2_clk_sync[2] & ~ps2_clk_sync[1];
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always @(posedge clk) begin
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if (resetn == 0) begin // reset
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count <= 0;
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end
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else begin
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if (sampling) begin
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if (count == 4'd10) begin
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if ((buffer[0] == 0) && // start bit
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(ps2_data) && // stop bit
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(^buffer[9:1])) begin // odd parity
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$display("recieve %x", buffer[8:1]);
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end
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count <= 0; // for next
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end else begin
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buffer[count] <= ps2_data; // store ps2_data
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count <= count + 3'b1;
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end
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end
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end
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end
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endmodule |