19 lines
361 B
Verilog
19 lines
361 B
Verilog
module led(
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input clk,
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input rst,
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input [7:0] sw,
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output [15:0] ledr
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);
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reg [31:0] count;
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reg [7:0] led;
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always @(posedge clk) begin
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if (rst) begin led <= 1; count <= 0; end
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else begin
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if (count == 0) led <= {led[6:0], led[7]};
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count <= (count >= 50000 ? 32'b0 : count + 1);
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end
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end
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assign ledr = {led, sw};
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endmodule
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