59 lines
1.3 KiB
Verilog
59 lines
1.3 KiB
Verilog
module vga_ctrl (
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input pclk,
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input reset,
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input [23:0] vga_data,
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output [9:0] h_addr,
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output [9:0] v_addr,
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output hsync,
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output vsync,
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output valid,
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output [7:0] vga_r,
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output [7:0] vga_g,
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output [7:0] vga_b
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);
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parameter h_frontporch = 96;
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parameter h_active = 144;
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parameter h_backporch = 784;
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parameter h_total = 800;
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parameter v_frontporch = 2;
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parameter v_active = 35;
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parameter v_backporch = 515;
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parameter v_total = 525;
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reg [9:0] x_cnt;
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reg [9:0] y_cnt;
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wire h_valid;
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wire v_valid;
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always @(posedge pclk) begin
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if(reset == 1'b1) begin
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x_cnt <= 1;
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y_cnt <= 1;
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end
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else begin
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if(x_cnt == h_total)begin
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x_cnt <= 1;
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if(y_cnt == v_total) y_cnt <= 1;
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else y_cnt <= y_cnt + 1;
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end
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else x_cnt <= x_cnt + 1;
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end
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end
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//生成同步信号
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assign hsync = (x_cnt > h_frontporch);
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assign vsync = (y_cnt > v_frontporch);
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//生成消隐信号
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assign h_valid = (x_cnt > h_active) & (x_cnt <= h_backporch);
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assign v_valid = (y_cnt > v_active) & (y_cnt <= v_backporch);
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assign valid = h_valid & v_valid;
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//计算当前有效像素坐标
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assign h_addr = h_valid ? (x_cnt - 10'd145) : 10'd0;
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assign v_addr = v_valid ? (y_cnt - 10'd36) : 10'd0;
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//设置输出的颜色值
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assign {vga_r, vga_g, vga_b} = vga_data;
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endmodule
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