example,vsrc,seg: display digits 0~7 to keep consistent with indices

This commit is contained in:
Zihao Yu 2022-02-26 15:47:42 +08:00
parent 6a4abfafaf
commit e9931cbd0f
2 changed files with 9 additions and 9 deletions

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@ -5,7 +5,7 @@
该示例的演示效果如下:
1. 左边8个LED为流水灯效果
1. 拨动右边的8个拨码开关, 可控制对应LED的亮灭
1. 8个数码管流水显示数字1-8
1. 8个数码管流水显示数字0-7
1. 按钮暂无展示效果
1. 窗口右侧为VGA输出, 将会展示一张图片
1. 敲击键盘, 终端将会输出按键的扫描码

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@ -12,14 +12,14 @@ module seg(
);
wire [7:0] segs [7:0];
assign segs[0] = 8'b01100001;
assign segs[1] = 8'b11011010;
assign segs[2] = 8'b11110010;
assign segs[3] = 8'b01100110;
assign segs[4] = 8'b10110110;
assign segs[5] = 8'b10111110;
assign segs[6] = 8'b11100000;
assign segs[7] = 8'b11111110;
assign segs[0] = 8'b11111101;
assign segs[1] = 8'b01100000;
assign segs[2] = 8'b11011010;
assign segs[3] = 8'b11110010;
assign segs[4] = 8'b01100110;
assign segs[5] = 8'b10110110;
assign segs[6] = 8'b10111110;
assign segs[7] = 8'b11100000;
parameter CLK_NUM = 5000000;