438 lines
16 KiB
C++
438 lines
16 KiB
C++
//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions. This pass should be run after register allocation but before
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// the post-regalloc scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVInstrInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/MC/MCContext.h"
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using namespace llvm;
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#define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
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#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISCV Pre-RA pseudo instruction expansion pass"
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namespace {
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class RISCVExpandPseudo : public MachineFunctionPass {
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public:
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const RISCVInstrInfo *TII;
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static char ID;
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RISCVExpandPseudo() : MachineFunctionPass(ID) {
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initializeRISCVExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned Opcode);
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bool expandVSPILL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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bool expandVRELOAD(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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};
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char RISCVExpandPseudo::ID = 0;
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bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
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// expanded instructions for each pseudo is correct in the Size field of the
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// tablegen definition for the pseudo.
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switch (MBBI->getOpcode()) {
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case RISCV::PseudoVSETVLI:
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case RISCV::PseudoVSETVLIX0:
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case RISCV::PseudoVSETIVLI:
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return expandVSetVL(MBB, MBBI);
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case RISCV::PseudoVMCLR_M_B1:
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case RISCV::PseudoVMCLR_M_B2:
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case RISCV::PseudoVMCLR_M_B4:
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case RISCV::PseudoVMCLR_M_B8:
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case RISCV::PseudoVMCLR_M_B16:
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case RISCV::PseudoVMCLR_M_B32:
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case RISCV::PseudoVMCLR_M_B64:
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// vmclr.m vd => vmxor.mm vd, vd, vd
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return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
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case RISCV::PseudoVMSET_M_B1:
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case RISCV::PseudoVMSET_M_B2:
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case RISCV::PseudoVMSET_M_B4:
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case RISCV::PseudoVMSET_M_B8:
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case RISCV::PseudoVMSET_M_B16:
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case RISCV::PseudoVMSET_M_B32:
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case RISCV::PseudoVMSET_M_B64:
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// vmset.m vd => vmxnor.mm vd, vd, vd
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return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
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case RISCV::PseudoVSPILL2_M1:
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case RISCV::PseudoVSPILL2_M2:
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case RISCV::PseudoVSPILL2_M4:
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case RISCV::PseudoVSPILL3_M1:
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case RISCV::PseudoVSPILL3_M2:
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case RISCV::PseudoVSPILL4_M1:
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case RISCV::PseudoVSPILL4_M2:
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case RISCV::PseudoVSPILL5_M1:
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case RISCV::PseudoVSPILL6_M1:
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case RISCV::PseudoVSPILL7_M1:
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case RISCV::PseudoVSPILL8_M1:
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return expandVSPILL(MBB, MBBI);
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case RISCV::PseudoVRELOAD2_M1:
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case RISCV::PseudoVRELOAD2_M2:
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case RISCV::PseudoVRELOAD2_M4:
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case RISCV::PseudoVRELOAD3_M1:
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case RISCV::PseudoVRELOAD3_M2:
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case RISCV::PseudoVRELOAD4_M1:
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case RISCV::PseudoVRELOAD4_M2:
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case RISCV::PseudoVRELOAD5_M1:
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case RISCV::PseudoVRELOAD6_M1:
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case RISCV::PseudoVRELOAD7_M1:
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case RISCV::PseudoVRELOAD8_M1:
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return expandVRELOAD(MBB, MBBI);
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}
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return false;
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}
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bool RISCVExpandPseudo::expandVSetVL(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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assert(MBBI->getNumExplicitOperands() == 3 && MBBI->getNumOperands() >= 5 &&
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"Unexpected instruction format");
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DebugLoc DL = MBBI->getDebugLoc();
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assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI ||
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MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
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MBBI->getOpcode() == RISCV::PseudoVSETIVLI) &&
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"Unexpected pseudo instruction");
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unsigned Opcode;
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if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI)
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Opcode = RISCV::VSETIVLI;
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else
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Opcode = RISCV::VSETVLI;
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const MCInstrDesc &Desc = TII->get(Opcode);
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assert(Desc.getNumOperands() == 3 && "Unexpected instruction format");
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Register DstReg = MBBI->getOperand(0).getReg();
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bool DstIsDead = MBBI->getOperand(0).isDead();
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BuildMI(MBB, MBBI, DL, Desc)
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.add(MBBI->getOperand(1)) // VL
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.add(MBBI->getOperand(2)); // VType
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MBBI->eraseFromParent(); // The pseudo instruction is gone now.
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return true;
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}
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bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned Opcode) {
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DebugLoc DL = MBBI->getDebugLoc();
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Register DstReg = MBBI->getOperand(0).getReg();
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const MCInstrDesc &Desc = TII->get(Opcode);
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BuildMI(MBB, MBBI, DL, Desc, DstReg)
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.addReg(DstReg, RegState::Undef)
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.addReg(DstReg, RegState::Undef);
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MBBI->eraseFromParent(); // The pseudo instruction is gone now.
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return true;
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}
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bool RISCVExpandPseudo::expandVSPILL(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getSubtarget().getRegisterInfo();
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DebugLoc DL = MBBI->getDebugLoc();
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Register SrcReg = MBBI->getOperand(0).getReg();
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Register Base = MBBI->getOperand(1).getReg();
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Register VL = MBBI->getOperand(2).getReg();
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auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MBBI->getOpcode());
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if (!ZvlssegInfo)
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return false;
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unsigned NF = ZvlssegInfo->first;
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unsigned LMUL = ZvlssegInfo->second;
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assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
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unsigned Opcode = RISCV::VS1R_V;
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unsigned SubRegIdx = RISCV::sub_vrm1_0;
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static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
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"Unexpected subreg numbering");
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if (LMUL == 2) {
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Opcode = RISCV::VS2R_V;
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SubRegIdx = RISCV::sub_vrm2_0;
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static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
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"Unexpected subreg numbering");
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} else if (LMUL == 4) {
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Opcode = RISCV::VS4R_V;
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SubRegIdx = RISCV::sub_vrm4_0;
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static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
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"Unexpected subreg numbering");
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} else
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assert(LMUL == 1 && "LMUL must be 1, 2, or 4.");
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for (unsigned I = 0; I < NF; ++I) {
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// Adding implicit-use of super register to describe we are using part of
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// super register, that prevents machine verifier complaining when part of
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// subreg is undef, see comment in MachineVerifier::checkLiveness for more
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// detail.
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BuildMI(MBB, MBBI, DL, TII->get(Opcode))
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.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
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.addReg(Base)
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.addMemOperand(*(MBBI->memoperands_begin()))
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.addReg(SrcReg, RegState::Implicit);
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if (I != NF - 1)
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)
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.addReg(Base)
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.addReg(VL);
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}
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MBBI->eraseFromParent();
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return true;
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}
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bool RISCVExpandPseudo::expandVRELOAD(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getSubtarget().getRegisterInfo();
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DebugLoc DL = MBBI->getDebugLoc();
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Register DestReg = MBBI->getOperand(0).getReg();
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Register Base = MBBI->getOperand(1).getReg();
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Register VL = MBBI->getOperand(2).getReg();
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auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MBBI->getOpcode());
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if (!ZvlssegInfo)
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return false;
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unsigned NF = ZvlssegInfo->first;
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unsigned LMUL = ZvlssegInfo->second;
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assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
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unsigned Opcode = RISCV::VL1RE8_V;
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unsigned SubRegIdx = RISCV::sub_vrm1_0;
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static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
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"Unexpected subreg numbering");
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if (LMUL == 2) {
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Opcode = RISCV::VL2RE8_V;
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SubRegIdx = RISCV::sub_vrm2_0;
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static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
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"Unexpected subreg numbering");
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} else if (LMUL == 4) {
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Opcode = RISCV::VL4RE8_V;
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SubRegIdx = RISCV::sub_vrm4_0;
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static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
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"Unexpected subreg numbering");
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} else
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assert(LMUL == 1 && "LMUL must be 1, 2, or 4.");
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for (unsigned I = 0; I < NF; ++I) {
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BuildMI(MBB, MBBI, DL, TII->get(Opcode),
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TRI->getSubReg(DestReg, SubRegIdx + I))
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.addReg(Base)
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.addMemOperand(*(MBBI->memoperands_begin()));
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if (I != NF - 1)
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)
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.addReg(Base)
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.addReg(VL);
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}
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MBBI->eraseFromParent();
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return true;
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}
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class RISCVPreRAExpandPseudo : public MachineFunctionPass {
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public:
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const RISCVInstrInfo *TII;
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static char ID;
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RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {
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initializeRISCVPreRAExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return RISCV_PRERA_EXPAND_PSEUDO_NAME;
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}
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandAuipcInstPair(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned FlagsHi, unsigned SecondOpcode);
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bool expandLoadLocalAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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};
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char RISCVPreRAExpandPseudo::ID = 0;
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bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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switch (MBBI->getOpcode()) {
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case RISCV::PseudoLLA:
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return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA:
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return expandLoadAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA_TLS_IE:
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return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA_TLS_GD:
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return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
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}
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return false;
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}
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bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
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unsigned SecondOpcode) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg =
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MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
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MachineOperand &Symbol = MI.getOperand(1);
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Symbol.setTargetFlags(FlagsHi);
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MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
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MachineInstr *MIAUIPC =
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
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MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
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MachineInstr *SecondMI =
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BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
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.addReg(ScratchReg)
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.addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
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if (MI.hasOneMemOperand())
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SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
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MI.eraseFromParent();
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return true;
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}
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bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
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RISCV::ADDI);
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}
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bool RISCVPreRAExpandPseudo::expandLoadAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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assert(MF->getTarget().isPositionIndependent());
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const auto &STI = MF->getSubtarget<RISCVSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
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SecondOpcode);
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}
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bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<RISCVSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
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SecondOpcode);
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}
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bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
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RISCV::ADDI);
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}
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} // end of anonymous namespace
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INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
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RISCV_EXPAND_PSEUDO_NAME, false, false)
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INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
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RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
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namespace llvm {
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FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
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FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
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} // end of namespace llvm
|