113 lines
3.8 KiB
C++
113 lines
3.8 KiB
C++
//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the RISCV target.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
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#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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// RISCV-specific code to select RISCV machine instructions for
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// SelectionDAG operations.
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namespace llvm {
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class RISCVDAGToDAGISel : public SelectionDAGISel {
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const RISCVSubtarget *Subtarget = nullptr;
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public:
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explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TargetMachine, OptLevel) {}
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StringRef getPassName() const override {
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return "RISCV DAG->DAG Pattern Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<RISCVSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void PostprocessISelDAG() override;
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void Select(SDNode *Node) override;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool tryShrinkShlLogicImm(SDNode *Node);
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bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
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bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) {
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return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
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}
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bool selectShiftMask32(SDValue N, SDValue &ShAmt) {
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return selectShiftMask(N, 32, ShAmt);
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}
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bool selectSExti32(SDValue N, SDValue &Val);
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bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
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template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
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return selectZExtBits(N, Bits, Val);
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}
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bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
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template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
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return selectSHXADDOp(N, ShAmt, Val);
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}
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bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
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template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
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return selectSHXADD_UWOp(N, ShAmt, Val);
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}
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bool hasAllNBitUsers(SDNode *Node, unsigned Bits) const;
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bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
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bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
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// Return the RISC-V condition code that matches the given DAG integer
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// condition code. The CondCode must be one of those supported by the RISC-V
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// ISA (see translateSetCCForBranch).
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static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unsupported CondCode");
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case ISD::SETEQ:
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return RISCVCC::COND_EQ;
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case ISD::SETNE:
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return RISCVCC::COND_NE;
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case ISD::SETLT:
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return RISCVCC::COND_LT;
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case ISD::SETGE:
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return RISCVCC::COND_GE;
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case ISD::SETULT:
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return RISCVCC::COND_LTU;
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case ISD::SETUGE:
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return RISCVCC::COND_GEU;
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}
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}
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// Include the pieces autogenerated from the target description.
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#include "RISCVGenDAGISel.inc"
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private:
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bool doPeepholeSExtW(SDNode *Node);
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};
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} // namespace llvm
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#endif
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