llvm-project/llvm/test/CodeGen
Craig Topper dc452a76c2 Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"
This reverts commit 82c820b95c.

This failed llvm-testsuite in our downstream and a similar issue
was reported by @rogfer01.
2022-11-01 20:04:07 -07:00
..
AArch64 [AArch64][GlobalISel] Add a simple cross-regclass copy optimization post-selection. 2022-11-01 16:09:21 -07:00
AMDGPU [AMDGPU] Fix RP tracker's live registers after processing a memory clause. 2022-11-01 11:47:59 +01:00
ARC [ARC] Regenerate ldst.ll 2022-10-29 14:09:58 +01:00
ARM [ARM] Tests for various NEON vector compares. NFC 2022-11-01 15:00:56 +00:00
AVR
BPF [llvm-objdump] Add --no-print-imm-hex to tests depending on it. 2022-10-29 15:40:26 -07:00
CSKY
DirectX [DirectX backend] set target triple to "dxil-ms-dx" 2022-10-24 14:49:31 -07:00
Generic [lit][REQUIRES] Fix some tests with incorrect REQUIRES clauses 2022-11-01 13:49:23 -07:00
Hexagon [lit][REQUIRES] Fix some tests with incorrect REQUIRES clauses 2022-11-01 13:49:23 -07:00
Inputs
Lanai
LoongArch [LoongArch] Support inline asm operand modifier 'z' 2022-10-31 09:56:41 +08:00
M68k [NFC][m68k] Add pipeline.ll 2022-10-31 08:52:46 +08:00
MIR MachineVerifier: Verify REG_SEQUENCE 2022-09-22 09:51:15 -04:00
MLRegalloc [mlgo] More wildcarding in extra features logging for regalloc 2022-10-25 08:20:55 -07:00
MSP430
Mips [llvm-objdump] Add --no-print-imm-hex to tests depending on it. 2022-10-29 15:40:26 -07:00
NVPTX [CUDA, NVPTX] Added basic __bf16 support for NVPTX. 2022-10-25 11:08:06 -07:00
PowerPC [lit][REQUIRES] Fix some tests with incorrect REQUIRES clauses 2022-11-01 13:49:23 -07:00
RISCV Revert "[RISCV] Enable the LocalStackSlotAllocation pass support" 2022-11-01 20:04:07 -07:00
SPARC [SPARC] Make calls to function with big return values work 2022-10-18 00:01:55 +00:00
SPIRV [SPIRV] support the enqueue_kernel builtin function 2022-11-01 02:52:08 +03:00
SystemZ SystemZ: Register null target streamer 2022-11-01 11:11:22 -07:00
Thumb [llvm-objdump] Add --no-print-imm-hex to tests depending on it. 2022-10-29 15:40:26 -07:00
Thumb2 Revert "[MachineCSE] Allow PRE of instructions that read physical registers" 2022-10-28 14:39:56 +01:00
VE [VE] Change the way to lower selectcc 2022-10-20 08:08:59 +09:00
WebAssembly Revert "Update supported features in the generic CPU configuration" 2022-10-25 16:34:08 -07:00
WinCFGuard
WinEH
X86 [X86] combineConcatVectorOps - fold 512-bit concat(GF2P8AFFINEQB(x,y,c),GF2P8AFFINEQB(z,w,c)) -> GF2P8AFFINEQB(concat(x,z),concat(y,w),c) 2022-11-01 12:06:46 +00:00
XCore XCore: Register null MCTargetStreamer 2022-11-01 11:11:03 -07:00