73 lines
2.4 KiB
C++
73 lines
2.4 KiB
C++
//===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "RISCVGenRegisterInfo.inc"
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namespace llvm {
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struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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RISCVRegisterInfo(unsigned HwMode);
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool isAsmClobberable(const MachineFunction &MF,
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MCRegister PhysReg) const override;
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const uint32_t *getNoPreservedMask() const override;
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bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
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int &FrameIdx) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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Register getFrameRegister(const MachineFunction &MF) const override;
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bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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return true;
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}
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override {
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return &RISCV::GPRRegClass;
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}
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &) const override;
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void getOffsetOpcodes(const StackOffset &Offset,
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SmallVectorImpl<uint64_t> &Ops) const override;
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unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
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};
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}
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#endif
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