llvm-project/llvm/test
Craig Topper d85e347a28 [RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
For strided accesses the loop vectorizer seems to prefer creating a
vector induction variable with a start value of the form
<i32 0, i32 1, i32 2, ...>. This value will be incremented each
loop iteration by a splat constant equal to the length of the vector.
Within the loop, arithmetic using splat values will be done on this
vector induction variable to produce indices for a vector GEP.

This pass attempts to dig through the arithmetic back to the phi
to create a new scalar induction variable and a stride. We push
all of the arithmetic out of the loop by folding it into the start,
step, and stride values. Then we create a scalar GEP to use as the
base pointer for a strided load or store using the computed stride.
Loop strength reduce will run after this pass and can do some
cleanups to the scalar GEP and induction variable.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D107790
2021-09-20 09:39:44 -07:00
..
Analysis Revert "[AArch64][SVE] Teach cost model that masked loads/stores are cheap" 2021-09-20 08:45:18 +00:00
Assembler [IR] Reduce max supported integer from 2^24-1 to 2^23. 2021-09-14 07:52:10 -07:00
Bindings
Bitcode [DebugInfo] Enhance DIImportedEntity to accept children entities 2021-09-16 10:41:55 +05:30
BugPoint
CodeGen [RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter. 2021-09-20 09:39:44 -07:00
DebugInfo llvm-dwarfdump: Pretty print names qualified/with scopes 2021-09-19 16:36:01 -07:00
Demangle
Examples [ORC] Temporarily remove the lljit-with-remote-debugging test. 2021-09-12 18:52:30 +10:00
ExecutionEngine [RuntimeDyld] Implemented relocation of TLS symbols in ELF 2021-09-06 10:27:43 +02:00
Feature
FileCheck [FileCheck] Use StringRef for MatchRegexp to fix crash. 2021-09-01 14:27:14 +02:00
Instrumentation [DFSan] Add force_zero_label abilist option to DFSan. This can be used as a work-around for overtainting. 2021-09-17 12:57:40 -07:00
Integer
JitListener
LTO
Linker Copy Elementtype Attribute to IR at Link step 2021-09-07 11:41:43 -07:00
MC [SystemZ] Recognize .machine directive in parser. 2021-09-17 12:03:54 +02:00
MachineVerifier Revert @llvm.isnan intrinsic patchset. 2021-09-02 13:53:56 +03:00
Object
ObjectYAML [WebAssembly] Convert to new "dylink.0" section format 2021-09-12 05:30:38 -07:00
Other [NewPM] Use a separate struct for ModuleMemorySanitizerPass 2021-09-16 14:58:42 +02:00
SafepointIRVerifier
Support
SymbolRewriter
TableGen [TableGen] Allow target specific flags for RegisterClass 2021-08-31 22:29:11 -04:00
ThinLTO/X86
Transforms [DSE] Add additional tests to cover review comments. 2021-09-20 17:06:04 +01:00
Unit
Verifier [Verifier] Verify scoped noalias metadata 2021-09-20 18:27:28 +02:00
YAMLParser
tools [update_mir_test_checks.py] Use -NEXT FileCheck directories 2021-09-20 12:55:56 +01:00
.clang-format
CMakeLists.txt
TestRunner.sh
lit.cfg.py Add extra check for llvm::Any::TypeId visibility 2021-09-15 08:32:55 +02:00
lit.site.cfg.py.in Add extra check for llvm::Any::TypeId visibility 2021-09-15 08:32:55 +02:00