102 lines
4.1 KiB
C++
102 lines
4.1 KiB
C++
//===-- RISCVFrameLowering.h - Define frame lowering for RISCV -*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class implements RISCV-specific bits of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
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#define LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
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#include "RISCV.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/Support/TypeSize.h"
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namespace llvm {
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class RISCVSubtarget;
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class RISCVFrameLowering : public TargetFrameLowering {
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public:
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explicit RISCVFrameLowering(const RISCVSubtarget &STI)
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: TargetFrameLowering(StackGrowsUp,
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/*StackAlignment=*/Align(16),
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/*LocalAreaOffset=*/0,
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/*TransientStackAlignment=*/Align(16)),
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STI(STI) {}
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg) const override;
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void processFunctionBeforeFrameFinalized(
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MachineFunction &MF,
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RegScavenger *RS = nullptr) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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bool hasFP(const MachineFunction &MF) const override;
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bool hasBP(const MachineFunction &MF) const;
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bool hasReservedCallFrame(const MachineFunction &MF) const override;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool storeRegToReg(const TargetRegisterInfo *TRI) const override;
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bool loadRegFromReg(const TargetRegisterInfo *TRI) const override;
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// Get the first stack adjustment amount for SplitSPAdjust.
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// Return 0 if we don't want to to split the SP adjustment in prologue and
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// epilogue.
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uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const;
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bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
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bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
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/// Get stack size for different stack ID
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uint64_t getStackSize(const MachineFunction &MF, RISCVStackID::Value ID) const;
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/// Frame Objects:
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/// fi#0: id=4 size=48, align=4, at location [SP+8]
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/// fi#1: id=1 size=4, align=4, at location [SP+4] \
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/// fi#2: id=1 size=4, align=4, at location [SP] \
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/// As we can see, if we split the stack, different frame offset calculation
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/// need to be modified too, when calculate the TP stack offset, we need to
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/// extract the stack offset of 'SP' in machine function frame
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uint64_t getStackOffset(const MachineFunction &MF, int FI,
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RISCVStackID::Value Stack) const;
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/// Before insert prolog/epilog information, set stack ID for each frame index
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void determineStackID(MachineFunction &MF) const;
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bool enableShrinkWrapping(const MachineFunction &MF) const override;
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bool isSupportedStackID(TargetStackID::Value ID) const override;
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protected:
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const RISCVSubtarget &STI;
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private:
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void determineFrameLayout(MachineFunction &MF) const;
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};
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} // namespace llvm
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#endif
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