| .. |
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GlobalISel
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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VentusGPGPU
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Merge pull request #49 from THU-DSP-LAB/instructions-remove
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2024-01-24 09:41:33 +08:00 |
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intrinsics
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…
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rvv
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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MachineSink-implicit-x0.mir
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Fix minor deficiency in machine-sink.
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2021-11-12 08:01:13 +01:00 |
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O0-pipeline.ll
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[X86] Add ExpandLargeFpConvert Pass and enable for X86
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2022-12-01 13:47:43 +08:00 |
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O3-pipeline.ll
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Revert "[CodeGen] Add new pass for late cleanup of redundant definitions."
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2022-12-01 13:29:24 -05:00 |
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add-before-shl.ll
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[RISCV] Use register allocation hints to improve use of compressed instructions.
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2022-11-25 08:39:44 -08:00 |
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add-imm.ll
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[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
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2022-06-24 08:31:52 -07:00 |
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addc-adde-sube-subc.ll
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…
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addcarry.ll
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[RISCV] Use register allocation hints to improve use of compressed instructions.
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2022-11-25 08:39:44 -08:00 |
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addimm-mulimm.ll
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[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
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2022-06-24 08:31:52 -07:00 |
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addrspacecast.ll
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…
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aext-to-sext.ll
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[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
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2022-11-30 10:28:57 -08:00 |
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align-loops.ll
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[CodeGen] Add -align-loops
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2021-08-04 12:45:18 -07:00 |
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align.ll
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…
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alloca.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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alu8.ll
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[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
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2022-07-14 16:10:14 -07:00 |
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alu16.ll
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[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
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2022-07-14 16:10:14 -07:00 |
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alu32.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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alu64.ll
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[RISCV] Use branchless form for selects with 0 in either arm
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2022-10-12 13:51:52 -07:00 |
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analyze-branch.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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and.ll
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[RISCV] Use register allocation hints to improve use of compressed instructions.
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2022-11-25 08:39:44 -08:00 |
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arith-with-overflow.ll
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…
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atomic-cmpxchg-branch-on-result.ll
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[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
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2022-08-17 13:49:15 +01:00 |
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atomic-cmpxchg-flag.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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atomic-cmpxchg.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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atomic-fence.ll
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…
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atomic-load-store.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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atomic-rmw.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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atomic-signext.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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attributes.ll
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[RISCV] Add CodeGen support and MC testcase of RISCV Zca Extension
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2022-11-22 17:22:26 +08:00 |
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bitreverse-shift.ll
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[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
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2022-03-30 11:46:42 -07:00 |
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bittest.ll
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[RISCV] Add ANDI to getRegAllocationHints.
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2022-11-30 20:59:02 -08:00 |
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blockaddress.ll
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…
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branch-relaxation.ll
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[RISCV] Fold low 12 bits into instruction during frame index elimination
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2022-12-02 11:54:06 -08:00 |
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branch.ll
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[RISCV] Add ANDI to getRegAllocationHints.
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2022-11-30 20:59:02 -08:00 |
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bswap-bitreverse.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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bswap-shift.ll
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[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
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2022-03-30 11:46:42 -07:00 |
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byval.ll
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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callee-saved-fpr32s.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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callee-saved-fpr64s.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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callee-saved-gprs.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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calling-conv-half.ll
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[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
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2022-11-30 10:28:57 -08:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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calling-conv-ilp32.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-ilp32d.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-ilp32f-ilp32d-common.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-lp64-lp64f-common.ll
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[RISCV] Use register allocation hints to improve use of compressed instructions.
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2022-11-25 08:39:44 -08:00 |
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calling-conv-lp64-lp64f-lp64d-common.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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calling-conv-lp64.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-rv32f-ilp32.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-sext-zext.ll
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…
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calling-conv-vector-float.ll
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[RISCV] Fix a crash when lowering split float arguments
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2021-07-22 09:55:26 +01:00 |
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calls.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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cmp-bool.ll
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…
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codemodel-lowering.ll
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[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
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2022-08-01 11:30:02 +02:00 |
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compress-float.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
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2021-11-25 07:21:42 -05:00 |
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compress-inline-asm.ll
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…
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compress-opt-branch.ll
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[RISCV] Optimization for using compressed beqz and bnez PR#56391
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2022-10-06 09:33:32 -07:00 |
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compress-opt-select.ll
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[RISCV] Use branchless form for selects with 0 in either arm
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2022-10-12 13:51:52 -07:00 |
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compress.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
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2021-11-25 07:21:42 -05:00 |
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copy-frameindex.mir
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llvm-reduce: Don't assert on functions which don't track liveness
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2022-06-07 10:00:25 -04:00 |
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copysign-casts.ll
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[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
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2022-11-30 10:28:57 -08:00 |
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ctlz-cttz-ctpop.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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disable-tail-calls.ll
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…
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disjoint.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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div-by-constant.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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div-pow2.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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div.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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div_minsize.ll
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[RISCV]Enable isIntDivCheap when attribute is minsize
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2022-07-27 18:22:51 +08:00 |
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double-arith-strict.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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double-arith.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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double-bitmanip-dagcombines.ll
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[RISCV] Select SRLI+SLLI for AND with leading ones mask
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2022-03-16 02:10:57 +00:00 |
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double-br-fcmp.ll
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[RISCV] Restore "Enable shrink wrap by default"
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2022-07-02 11:13:13 +08:00 |
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double-calling-conv.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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double-convert-strict.ll
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[RISCV] Optimize SELECT_CC when the true value of select is Constant
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2022-10-18 09:24:17 +08:00 |
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double-convert.ll
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[RISCV] Use register allocation hints to improve use of compressed instructions.
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2022-11-25 08:39:44 -08:00 |
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double-fcmp-strict.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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double-fcmp.ll
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[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
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2022-07-13 19:37:34 +01:00 |
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double-frem.ll
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[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
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2022-08-10 10:50:29 +01:00 |
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double-imm.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-intrinsics-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-intrinsics.ll
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[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
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2022-10-26 14:36:49 -07:00 |
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double-isnan.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-mem.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-previous-failure.ll
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[RISCV] Teach combineDeMorganOfBoolean to handle (and (xor X, 1), (not Y)).
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2022-08-25 10:55:45 -07:00 |
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double-round-conv-sat.ll
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[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
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2022-10-13 09:06:12 -07:00 |
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double-round-conv.ll
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[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
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2022-10-26 14:36:49 -07:00 |
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double-select-fcmp.ll
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[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
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2022-08-17 09:50:08 -07:00 |
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double-select-icmp.ll
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[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
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2022-08-16 21:28:26 -07:00 |
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double-stack-spill-restore.ll
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[RISCV] Restore "Enable shrink wrap by default"
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2022-07-02 11:13:13 +08:00 |
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dwarf-eh.ll
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…
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early-clobber-tied-def-subreg-liveness.ll
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[RISCV][InsertVSETVLI] Default to MA not MU
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2022-10-06 07:59:39 -07:00 |
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early-clobber-tied-def-subreg-liveness.mir
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Reland "[SplitKit] Handle early clobber + tied to def correctly"
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2022-06-16 17:13:09 +08:00 |
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eh-dwarf-cfa.ll
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[RISCV] Add ISD::EH_DWARF_CFA
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2022-06-08 22:03:30 +08:00 |
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elf-preemption.ll
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[RISCV] Pre-RA expand pseudos pass
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2022-07-31 23:19:00 +02:00 |
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exception-pointer-register.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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fastcc-float.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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fastcc-int.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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fixups-diff.ll
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…
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fixups-relax-diff.ll
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…
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float-arith-strict.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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float-arith.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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float-bit-preserving-dagcombines.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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float-bitmanip-dagcombines.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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float-br-fcmp.ll
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[RISCV] Restore "Enable shrink wrap by default"
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2022-07-02 11:13:13 +08:00 |
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float-convert-strict.ll
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[RISCV] Optimize SELECT_CC when the true value of select is Constant
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2022-10-18 09:24:17 +08:00 |
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float-convert.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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float-fcmp-strict.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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float-fcmp.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-frem.ll
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[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
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2021-11-11 10:56:27 -08:00 |
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float-imm.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-intrinsics-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-intrinsics.ll
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[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
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2022-10-26 14:36:49 -07:00 |
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float-isnan.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-mem.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-round-conv-sat.ll
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[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
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2022-10-26 14:36:49 -07:00 |
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float-round-conv.ll
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[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
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2022-10-26 14:36:49 -07:00 |
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float-select-fcmp.ll
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[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
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2022-08-17 09:50:08 -07:00 |
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float-select-icmp.ll
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[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
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2022-08-16 21:28:26 -07:00 |
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flt-rounds.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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fmax-fmin.ll
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[SDAG] avoid libcalls to fmin/fmax for soft-float targets
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2022-03-30 11:22:03 -04:00 |
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fold-addi-loadstore.ll
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[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
|
2022-08-01 11:30:02 +02:00 |
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fold-vector-cmp.ll
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[RISCV] Use register allocation hints to improve use of compressed instructions.
|
2022-11-25 08:39:44 -08:00 |
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forced-atomics.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
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2022-12-01 11:09:38 -08:00 |
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fp-imm.ll
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[RISCV] Optimize lowering of floating-point -0.0
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2022-01-20 11:46:28 +00:00 |
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fp16-promote.ll
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[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
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2022-08-10 10:50:29 +01:00 |
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fp128.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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fpclamptosat.ll
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[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
|
2022-10-13 09:06:12 -07:00 |
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fpclamptosat_vec.ll
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[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
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fpenv.ll
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[RISCV] Add shift amount operands of shift, rotate, and Zbs instructions to hasAllNBitUsers.
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2022-10-24 22:07:22 -07:00 |
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frame-info.ll
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[RISCV] Restore "Enable shrink wrap by default"
|
2022-07-02 11:13:13 +08:00 |
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frame.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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frameaddr-returnaddr.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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frm-dependency.ll
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[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
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get-register-invalid.ll
|
…
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|
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get-register-noreserve.ll
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[RISCV] Add llvm.read.register support for vlenb
|
2022-05-13 09:12:02 -07:00 |
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get-register-reserve.ll
|
…
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get-setcc-result-type.ll
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Recommit "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
|
2022-08-16 15:51:07 -07:00 |
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ghccc-nest.ll
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[RISCV] Add support for static chain
|
2022-11-09 16:10:32 +08:00 |
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ghccc-rv32.ll
|
…
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|
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ghccc-rv64.ll
|
…
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|
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global-merge-offset.ll
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[RISCV] Add the GlobalMerge pass (disabled by default)
|
2022-09-08 18:40:38 -07:00 |
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global-merge.ll
|
[RISCV] Add the GlobalMerge pass (disabled by default)
|
2022-09-08 18:40:38 -07:00 |
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half-arith-strict.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-arith.ll
|
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
|
2022-11-30 10:28:57 -08:00 |
|
half-bitmanip-dagcombines.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-br-fcmp.ll
|
[RISCV] Restore "Enable shrink wrap by default"
|
2022-07-02 11:13:13 +08:00 |
|
half-convert-strict.ll
|
[RISCV] Optimize SELECT_CC when the true value of select is Constant
|
2022-10-18 09:24:17 +08:00 |
|
half-convert.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
half-fcmp-strict.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
half-fcmp.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
half-frem.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-imm.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-intrinsics.ll
|
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
|
2022-10-26 14:36:49 -07:00 |
|
half-isnan.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-mem.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-round-conv-sat.ll
|
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
|
2022-10-26 14:36:49 -07:00 |
|
half-round-conv.ll
|
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
|
2022-10-26 14:36:49 -07:00 |
|
half-select-fcmp.ll
|
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
|
2022-08-17 09:50:08 -07:00 |
|
half-select-icmp.ll
|
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
|
2022-08-16 21:28:26 -07:00 |
|
hoist-global-addr-base.ll
|
[RISCV] Simplify test case from D130931. NFC
|
2022-08-01 16:50:56 -07:00 |
|
hwasan-check-memaccess.ll
|
[RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V
|
2022-08-28 21:22:13 +03:00 |
|
i32-icmp.ll
|
[RISCV] Use SLTIU X, -1 for (setne X, -1).
|
2022-08-11 15:36:04 -07:00 |
|
i64-icmp.ll
|
[RISCV] Use SLTIU X, -1 for (setne X, -1).
|
2022-08-11 15:36:04 -07:00 |
|
iabs.ll
|
[RISCV] Expand i32 abs to negw+max at isel.
|
2022-11-14 19:44:05 -08:00 |
|
imm-cse.ll
|
…
|
|
|
imm.ll
|
[RISCV] Use register allocation hints to improve use of compressed instructions.
|
2022-11-25 08:39:44 -08:00 |
|
indirectbr.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
init-array.ll
|
…
|
|
|
inline-asm-S-constraint.ll
|
[RISCV] Support machine constraint "S"
|
2021-07-13 09:30:09 -07:00 |
|
inline-asm-abi-names.ll
|
…
|
|
|
inline-asm-clobbers.ll
|
[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
|
inline-asm-d-abi-names.ll
|
…
|
|
|
inline-asm-d-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm-f-abi-names.ll
|
…
|
|
|
inline-asm-f-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm-i-constraint-i1.ll
|
…
|
|
|
inline-asm-invalid.ll
|
[RISCV] Don't allow vector types to be used with inline asm 'r' constraint
|
2021-12-23 20:32:36 -06:00 |
|
inline-asm-zfh-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm.ll
|
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
|
2022-01-06 08:13:42 -08:00 |
|
interrupt-attr-args-error.ll
|
…
|
|
|
interrupt-attr-callee.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
interrupt-attr-invalid.ll
|
…
|
|
|
interrupt-attr-nocall.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
interrupt-attr-ret-error.ll
|
…
|
|
|
interrupt-attr.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
isel-optnone.ll
|
[RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly
|
2022-05-30 17:22:50 -07:00 |
|
jumptable.ll
|
[RISCV] Pre-RA expand pseudos pass
|
2022-07-31 23:19:00 +02:00 |
|
large-stack.ll
|
[RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer constants)
|
2022-11-30 09:28:29 -08:00 |
|
legalize-fneg.ll
|
[RISCV] Teach targetShrinkDemandedConstant to handle OR and XOR.
|
2022-07-17 12:36:33 -07:00 |
|
libcall-tail-calls.ll
|
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
|
2022-08-10 10:50:29 +01:00 |
|
lit.local.cfg
|
…
|
|
|
live-sp.mir
|
[RISCV] Fix invalid kill on callee save
|
2021-11-02 11:56:54 +00:00 |
|
local-stack-slot-allocation.ll
|
[RISCV] Fold low 12 bits into instruction during frame index elimination
|
2022-12-02 11:54:06 -08:00 |
|
loop-strength-reduce-add-cheaper-than-mul.ll
|
[RISCV] Adjust RV64I data layout by using n32:64 in layout string
|
2022-10-28 08:27:03 -07:00 |
|
loop-strength-reduce-loop-invar.ll
|
[RISCV] Adjust RV64I data layout by using n32:64 in layout string
|
2022-10-28 08:27:03 -07:00 |
|
lsr-legaladdimm.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
machine-combiner-mir.ll
|
[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns
|
2022-11-17 13:24:04 +03:00 |
|
machine-combiner.ll
|
[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns
|
2022-11-17 13:24:04 +03:00 |
|
machine-cp.mir
|
[MachineCopyPropagation][RISCV] Fix D125335 accidentally change control flow.
|
2022-06-17 21:40:08 -07:00 |
|
machine-cse.ll
|
[RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ.
|
2022-05-02 20:21:16 -07:00 |
|
machine-outliner-cfi.mir
|
[RISCV] Precommit test for D122634
|
2022-04-22 12:19:55 +08:00 |
|
machine-outliner-patchable.ll
|
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
|
2021-12-13 13:24:29 -08:00 |
|
machine-outliner-position.mir
|
[RISCV] Precommit test for D122634
|
2022-04-22 12:19:55 +08:00 |
|
machine-outliner-throw.ll
|
[RISCV] Do not outline CFI instructions when they are needed in EH
|
2022-04-22 12:28:19 +08:00 |
|
machinelicm-address-pseudos.ll
|
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
|
2022-08-01 11:30:02 +02:00 |
|
machineoutliner-jumptable.mir
|
[RISCV] Fix Machine Outliner jump table handling.
|
2021-09-09 07:32:30 +02:00 |
|
machineoutliner-pcrel-lo.mir
|
[RISCV] Don't outline pcrel-lo operand.
|
2022-08-24 21:47:46 +08:00 |
|
machineoutliner.mir
|
…
|
|
|
macro-fusion-lui-addi.ll
|
[RISCV] Add macrofusion infrastructure and one example usage.
|
2022-06-23 08:38:39 -07:00 |
|
make-compressible-for-store-address.mir
|
[RISCV] Fix wrong register rename for store value during make-compressible optimization
|
2022-07-08 18:07:17 +08:00 |
|
make-compressible-rv64.mir
|
[RISCV] Add pre-emit pass to make more instructions compressible
|
2022-05-25 09:25:02 +01:00 |
|
make-compressible.mir
|
[RISCV] Add pre-emit pass to make more instructions compressible
|
2022-05-25 09:25:02 +01:00 |
|
mattr-invalid-combination.ll
|
[RISCV] Remove check and update test file in D121183
|
2022-03-24 00:48:52 +08:00 |
|
mem.ll
|
[RISCV] Add tests for (load (add X, [2048,4094])). NFC
|
2022-06-27 13:42:57 -07:00 |
|
mem64.ll
|
[RISCV] Make custom isel for (add X, imm) used by load/stores more selective.
|
2022-06-30 14:20:11 -07:00 |
|
memcpy-inline.ll
|
[RISCV] Teach shouldConvertConstantLoadToIntImm that constant materialization can use constant pools.
|
2022-07-10 14:10:17 -07:00 |
|
min-max.ll
|
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
|
2022-10-13 09:06:12 -07:00 |
|
mir-target-flags.ll
|
[RISCV] Pre-RA expand pseudos pass
|
2022-07-31 23:19:00 +02:00 |
|
miss-sp-restore-eh.ll
|
[RISCV] Fix missing stack pointer recover
|
2022-06-09 23:38:50 +08:00 |
|
module-target-abi.ll
|
…
|
|
|
module-target-abi2.ll
|
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
|
2022-03-24 00:48:52 +08:00 |
|
module-target-abi3.ll
|
[RISCV] Generate correct ELF abi flag when empty .ll file has target-abi attribute
|
2022-08-26 14:39:39 +08:00 |
|
mul.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
musttail-call.ll
|
…
|
|
|
narrow-shl-cst.ll
|
[RISCV] Use register allocation hints to improve use of compressed instructions.
|
2022-11-25 08:39:44 -08:00 |
|
neg-abs.ll
|
[RISCV] Expand i32 abs to negw+max at isel.
|
2022-11-14 19:44:05 -08:00 |
|
nest-register.ll
|
[RISCV] Add support for static chain
|
2022-11-09 16:10:32 +08:00 |
|
nomerge.ll
|
…
|
|
|
option-nopic.ll
|
…
|
|
|
option-norelax.ll
|
…
|
|
|
option-norvc.ll
|
…
|
|
|
option-pic.ll
|
…
|
|
|
option-relax.ll
|
…
|
|
|
option-rvc.ll
|
…
|
|
|
optnone-store-no-combine.ll
|
[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
|
2021-12-23 10:48:28 +05:30 |
|
out-of-reach-emergency-slot.mir
|
[RISCV] Fold low 12 bits into instruction during frame index elimination
|
2022-12-02 11:54:06 -08:00 |
|
overflow-intrinsic-optimizations.ll
|
[RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3()
|
2021-08-31 11:23:56 -07:00 |
|
patchable-function-entry.ll
|
…
|
|
|
pic-models.ll
|
[RISCV] Pre-RA expand pseudos pass
|
2022-07-31 23:19:00 +02:00 |
|
pr40333.ll
|
…
|
|
|
pr51206.ll
|
[RISCV] Use MULHU for more division by constant cases.
|
2021-12-09 09:10:14 -08:00 |
|
pr53662.mir
|
[RISCV] Don't getDebugLoc for the end node of MBB iterator
|
2022-04-30 16:00:20 +08:00 |
|
pr55201.ll
|
[DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask.
|
2022-04-30 11:02:30 -07:00 |
|
pr56110.ll
|
[DAGCombiner][ARM][RISCV] Teach ShrinkLoadReplaceStoreWithStore to use truncstore.
|
2022-06-19 15:50:15 -07:00 |
|
pr56457.ll
|
[TargetLowering][RISCV] Make expandCTLZ work for non-power of 2 types.
|
2022-07-12 11:36:37 -07:00 |
|
pr58025.ll
|
[RISCV][SelectionDAGBuilder] Fix crash when copying a v1f32 vector between basic blocks.
|
2022-09-28 10:13:35 -07:00 |
|
pr58286.ll
|
[RISCV] Fold low 12 bits into instruction during frame index elimination
|
2022-12-02 11:54:06 -08:00 |
|
pr58511.ll
|
[DAGCombiner][RISCV] Make foldBinOpIntoSelect work correctly with opaque constants.
|
2022-10-22 19:10:33 -07:00 |
|
prefetch.ll
|
[IR] Update llvm.prefetch to match docs
|
2022-08-19 09:11:17 +01:00 |
|
readcyclecounter.ll
|
…
|
|
|
regalloc-last-chance-recoloring-failure.ll
|
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
|
2022-10-11 16:40:16 -07:00 |
|
rem.ll
|
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
|
2022-08-10 10:50:29 +01:00 |
|
remat.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
reserved-reg-errors.ll
|
…
|
|
|
reserved-regs.ll
|
…
|
|
|
riscv-codegenprepare-asm.ll
|
[RISCV] Use register allocation hints to improve use of compressed instructions.
|
2022-11-25 08:39:44 -08:00 |
|
riscv-codegenprepare.ll
|
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
|
2022-07-17 11:00:56 -07:00 |
|
rotl-rotr.ll
|
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
|
2022-11-25 08:59:27 -08:00 |
|
rv32e.ll
|
…
|
|
|
rv32i-rv64i-float-double.ll
|
[NFC][llvm] Inclusive language: reword uses of sanity test and check
|
2021-11-25 07:21:42 -05:00 |
|
rv32i-rv64i-half.ll
|
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
|
2022-01-29 00:01:00 +08:00 |
|
rv32zba.ll
|
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
|
2022-11-25 08:59:27 -08:00 |
|
rv32zbb-intrinsic.ll
|
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
|
2022-03-28 16:56:33 -07:00 |
|
rv32zbb-zbkb.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
rv32zbb.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
rv32zbc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbc-zbkc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbkb-intrinsic.ll
|
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
|
2022-01-30 12:41:09 -08:00 |
|
rv32zbkb.ll
|
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
|
2022-11-30 10:28:57 -08:00 |
|
rv32zbkx-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbs.ll
|
[RISCV] Use register allocation hints to improve use of compressed instructions.
|
2022-11-25 08:39:44 -08:00 |
|
rv32zknd-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv32zkne-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv32zknh-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv32zksed-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv32zksh-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64-large-stack.ll
|
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
|
2021-07-20 09:22:06 -07:00 |
|
rv64d-double-convert-strict.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
rv64d-double-convert.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
rv64f-float-convert-strict.ll
|
[RISCV] Set target-abi explicitly to reduce codegen results
|
2022-06-01 13:49:23 +08:00 |
|
rv64f-float-convert.ll
|
[RISCV] Set target-abi explicitly to reduce codegen results
|
2022-06-01 13:49:23 +08:00 |
|
rv64i-complex-float.ll
|
[RISCV] Use register allocation hints to improve use of compressed instructions.
|
2022-11-25 08:39:44 -08:00 |
|
rv64i-demanded-bits.ll
|
[RISCV] Use hasAllWUsers to recover XORI/ORI
|
2022-10-10 14:16:50 +08:00 |
|
rv64i-double-softfloat.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
rv64i-exhaustive-w-insts.ll
|
[RISCV][NFC] Remove solved TODO for combining constant shifts
|
2022-05-26 09:55:19 +08:00 |
|
rv64i-shift-sext.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
rv64i-single-softfloat.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
rv64i-tricky-shifts.ll
|
…
|
|
|
rv64i-w-insts-legalization.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv64m-exhaustive-w-insts.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64m-w-insts-legalization.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv64zba.ll
|
[RISCV] Add isel patterns to select slli+shXadd.uw.
|
2022-11-21 09:32:51 -08:00 |
|
rv64zbb-intrinsic.ll
|
[RISCV] Remove support for the unratified Zbp extension.
|
2022-09-21 21:22:42 -07:00 |
|
rv64zbb-zbkb.ll
|
[RISCV] Add shift amount operands of shift, rotate, and Zbs instructions to hasAllNBitUsers.
|
2022-10-24 22:07:22 -07:00 |
|
rv64zbb.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
rv64zbc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbc-zbkc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbkb-intrinsic.ll
|
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
|
2022-01-30 12:41:09 -08:00 |
|
rv64zbkb.ll
|
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
|
2022-11-30 10:28:57 -08:00 |
|
rv64zbkx-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbs.ll
|
[RISCV] Add a DAG combine to pre-promote (i1 (truncate (i32 (srl X, Y)))) with Zbs on RV64.
|
2022-11-16 19:07:33 -08:00 |
|
rv64zfh-half-convert-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
rv64zfh-half-convert.ll
|
[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
|
2022-02-24 09:19:01 -08:00 |
|
rv64zfh-half-intrinsics.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
rv64zknd-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv64zknd-zkne-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv64zkne-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv64zknh-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv64zksed-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zksh-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
sadd_sat.ll
|
[RISCV] Remove support for the unratified Zbt extension.
|
2022-09-20 20:26:48 -07:00 |
|
sadd_sat_plus.ll
|
[RISCV] Remove support for the unratified Zbt extension.
|
2022-09-20 20:26:48 -07:00 |
|
saverestore.ll
|
…
|
|
|
scalable-vector-struct.ll
|
[RISCV] Remove experimental prefix from rvv-related extensions.
|
2022-01-22 20:18:40 -08:00 |
|
sdata-limit-0.ll
|
…
|
|
|
sdata-limit-4.ll
|
…
|
|
|
sdata-limit-8.ll
|
…
|
|
|
sdata-local-sym.ll
|
…
|
|
|
select-and.ll
|
[RISCV] Remove support for the unratified Zbt extension.
|
2022-09-20 20:26:48 -07:00 |
|
select-bare.ll
|
[RISCV] Remove support for the unratified Zbt extension.
|
2022-09-20 20:26:48 -07:00 |
|
select-binop-identity.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
select-cc.ll
|
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
|
2022-10-04 15:39:10 -07:00 |
|
select-const.ll
|
[RISCV] Branchless lowering for (select (x < 0), TrueConstant, FalseConstant) and (select (x >= 0), TrueConstant, FalseConstant)
|
2022-11-25 20:18:30 +08:00 |
|
select-constant-xor.ll
|
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
|
2022-11-30 10:28:57 -08:00 |
|
select-optimize-multiple.ll
|
[RISCV] Add ANDI to getRegAllocationHints.
|
2022-11-30 20:59:02 -08:00 |
|
select-optimize-multiple.mir
|
[RISCV] Remove support for the unratified Zbt extension.
|
2022-09-20 20:26:48 -07:00 |
|
select-or.ll
|
[RISCV] Remove support for the unratified Zbt extension.
|
2022-09-20 20:26:48 -07:00 |
|
select.ll
|
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
|
2022-11-30 10:28:57 -08:00 |
|
selectcc-to-shiftand.ll
|
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
|
2022-10-13 09:06:12 -07:00 |
|
setcc-logic.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
sext-zext-trunc.ll
|
[RISCV] Remove C!=0 restriction from (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)).
|
2022-08-16 14:49:52 -07:00 |
|
sextw-removal.ll
|
[RISCV] Fix incorrect early out from isSignExtendedW in RISCVSExtWRemoval.
|
2022-11-13 17:30:39 -08:00 |
|
shadowcallstack.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
shift-and.ll
|
[RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel.
|
2022-10-22 14:30:13 -07:00 |
|
shift-masked-shamt.ll
|
[RISCV] Add shift amount operands of shift, rotate, and Zbs instructions to hasAllNBitUsers.
|
2022-10-24 22:07:22 -07:00 |
|
shifts.ll
|
[RISCV] Use register allocation hints to improve use of compressed instructions.
|
2022-11-25 08:39:44 -08:00 |
|
shl-demanded.ll
|
[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
|
2022-07-14 16:10:14 -07:00 |
|
shlimm-addimm.ll
|
[RISCV][test] Add tests of (add (shl r, c0), c1)
|
2021-10-14 14:53:03 +00:00 |
|
short-foward-branch-opt.ll
|
[RISCV] Add basic support for the sifive-7-series short forward branch optimization.
|
2022-10-17 13:56:22 -07:00 |
|
shrinkwrap.ll
|
[RISCV] Restore "Enable shrink wrap by default"
|
2022-07-02 11:13:13 +08:00 |
|
shuffle-reverse.ll
|
[RISCV][InsertVSETVLI] Default to MA not MU
|
2022-10-06 07:59:39 -07:00 |
|
sink-icmp.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
spill-fpr-scalar.ll
|
[RISCV][InsertVSETVLI] Default to MA not MU
|
2022-10-06 07:59:39 -07:00 |
|
split-offsets.ll
|
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
|
2022-11-25 08:59:27 -08:00 |
|
split-sp-adjust.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
split-udiv-by-constant.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
split-urem-by-constant.ll
|
Recommit "[TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant."
|
2022-10-24 10:08:50 -07:00 |
|
srem-lkk.ll
|
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
|
2022-08-10 10:50:29 +01:00 |
|
srem-seteq-illegal-types.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
srem-vector-lkk.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
ssub_sat.ll
|
[RISCV] Remove support for the unratified Zbt extension.
|
2022-09-20 20:26:48 -07:00 |
|
ssub_sat_plus.ll
|
[RISCV] Remove support for the unratified Zbt extension.
|
2022-09-20 20:26:48 -07:00 |
|
stack-folding.ll
|
[RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl.
|
2022-07-21 14:54:58 -07:00 |
|
stack-realignment-with-variable-sized-objects.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
stack-realignment.ll
|
Revert "[CodeGen] Add new pass for late cleanup of redundant definitions."
|
2022-12-01 13:29:24 -05:00 |
|
stack-slot-size.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
stack-store-check.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
subtarget-features-std-ext.ll
|
…
|
|
|
switch-width.ll
|
[riscv] Add a bunch of tests exploring switch lowering
|
2022-05-11 13:16:31 -07:00 |
|
tail-calls.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
target-abi-invalid.ll
|
…
|
|
|
target-abi-valid.ll
|
…
|
|
|
thread-pointer.ll
|
…
|
|
|
tls-models.ll
|
[RISCV] Pre-RA expand pseudos pass
|
2022-07-31 23:19:00 +02:00 |
|
trunc-free.ll
|
[RISCV] Enable isTruncateFree in SDAG for i64->i32 on rv64.
|
2022-08-15 08:32:51 -07:00 |
|
uadd_sat.ll
|
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
|
2022-10-13 09:06:12 -07:00 |
|
uadd_sat_plus.ll
|
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
|
2022-11-25 08:59:27 -08:00 |
|
umulo-128-legalisation-lowering.ll
|
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
|
2022-11-25 08:59:27 -08:00 |
|
unaligned-load-store.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
unfold-masked-merge-scalar-variablemask.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
unroll-loop-cse.ll
|
Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"
|
2022-02-17 17:27:37 +08:00 |
|
urem-lkk.ll
|
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
|
2022-08-10 10:50:29 +01:00 |
|
urem-seteq-illegal-types.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
urem-vector-lkk.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
usub_sat.ll
|
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
|
2022-10-13 09:06:12 -07:00 |
|
usub_sat_plus.ll
|
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
|
2022-10-13 09:06:12 -07:00 |
|
vadd-vp-mask.ll
|
[RISCV][InsertVSETVLI] Default to MA not MU
|
2022-10-06 07:59:39 -07:00 |
|
vararg.ll
|
[RISCV] Fold low 12 bits into instruction during frame index elimination
|
2022-12-02 11:54:06 -08:00 |
|
vec3-setcc-crash.ll
|
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
|
2022-10-13 09:06:12 -07:00 |
|
vector-abi.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
verify-instr.mir
|
…
|
|
|
vlenb.ll
|
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)
|
2022-05-16 16:38:30 -07:00 |
|
vmul-vp-mask.ll
|
[RISCV][InsertVSETVLI] Default to MA not MU
|
2022-10-06 07:59:39 -07:00 |
|
vsub-vp-mask.ll
|
[RISCV][InsertVSETVLI] Default to MA not MU
|
2022-10-06 07:59:39 -07:00 |
|
wide-mem.ll
|
…
|
|
|
xaluo.ll
|
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
|
2022-12-01 11:09:38 -08:00 |
|
zext-with-load-is-free.ll
|
[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.
|
2022-05-27 11:05:18 -07:00 |
|
zfh-half-intrinsics-strict.ll
|
[LegalizeTypes][RISCV] Support f16 in ExpandIntRes_LLROUND_LLRINT.
|
2022-09-26 11:09:33 -07:00 |
|
zfh-half-intrinsics.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
zfh-imm.ll
|
[RISCV] Optimize lowering of floating-point -0.0
|
2022-01-20 11:46:28 +00:00 |
|
zmmul.ll
|
[RISCV][Clang] Add support for Zmmul extension
|
2022-07-18 20:26:08 -04:00 |
a87bae445c