llvm-project/llvm/test/CodeGen/AArch64
Simon Pilgrim dc681bc2e0 [AArch64] Regenerate arm64-vector-ldst.ll test checks 2022-07-16 15:27:47 +01:00
..
GlobalISel [GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT. 2022-07-14 11:05:10 -07:00
2s-complement-asm.ll
128bit_load_store.ll
DAGCombine_vscale.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
O0-pipeline.ll [CodeGen] Async unwind - add a pass to fix CFI information 2022-04-11 13:27:26 +01:00
O3-pipeline.ll Revert "[Propeller] Promote functions with propeller profiles to .text.hot." 2022-05-26 18:45:40 -07:00
PBQP-chain.ll
PBQP-coalesce-benefit.ll
PBQP-csr.ll
PBQP.ll
PHIElimination-crash.mir
PHIElimination-debugloc.mir
README
Redundantstore.ll
a55-fuse-address.mir [AArch64] Improve schedule modelling on the Cortex-A55 2021-09-21 13:03:34 +01:00
a57-csel.ll
aarch-multipart.ll
aarch64-2014-08-11-MachineCombinerCrash.ll
aarch64-2014-12-02-combine-soften.ll
aarch64-DAGCombine-findBetterNeighborChains-crash.ll
aarch64-a57-fp-load-balancing.ll
aarch64-address-type-promotion-assertion.ll
aarch64-address-type-promotion.ll
aarch64-addv.ll [AArch64] Reassociate integer extending reductions to pairwise addition. 2022-02-03 11:05:48 +00:00
aarch64-avoid-illegal-extract-subvector.ll [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR 2021-08-25 19:33:39 +08:00
aarch64-be-bv.ll AArch64: add nvcast patterns for v1f64 2022-04-11 12:24:48 +01:00
aarch64-bf16-dotprod-intrinsics.ll
aarch64-bf16-ldst-intrinsics.ll
aarch64-bif-gen.ll
aarch64-bit-gen.ll
aarch64-bswap-ext.ll
aarch64-checkMergeStoreCandidatesForDependencies.ll [DAGCombiner] Fix dependency analysis in checkMergeStoreCandidatesForDependencies 2022-02-04 08:53:01 +01:00
aarch64-codegen-prepare-atp.ll
aarch64-combine-fmul-fsub.mir [MachineCombiner] Don't compute the latency of transient instructions 2022-07-14 17:08:14 +00:00
aarch64-dup-ext-crash.ll [AArch64] Regenerate some test checks. NFC 2021-09-08 11:08:32 +01:00
aarch64-dup-ext-scalable.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
aarch64-dup-ext-vectortype-crash.ll
aarch64-dup-ext.ll [AArch64] Alter mull buildvectors(ext(..)) combine to work on shuffles 2022-04-04 23:07:47 +01:00
aarch64-dup-extract-scalable.ll
aarch64-dynamic-stack-layout.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
aarch64-fix-cortex-a53-835769.ll [AArch64] Use Feature for A53 Erratum 835769 Fix 2021-12-10 15:09:59 +00:00
aarch64-fold-lslfast.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
aarch64-gep-opt.ll
aarch64-insert-subvector-undef.ll
aarch64-interleaved-ld-combine.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
aarch64-isel-csinc-type.ll [DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction 2022-02-16 09:39:38 +08:00
aarch64-isel-csinc.ll [DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction 2022-02-16 09:39:38 +08:00
aarch64-ldst-modified-baseReg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-ldst-no-premature-sp-pop.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-ldst-subsuperReg-no-ldp.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-load-ext.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
aarch64-loop-gep-opt.ll
aarch64-lsr-bfi.ll [AArch64] Fold lsr+bfi in tryBitfieldInsertOpFromOr 2022-04-06 22:02:31 +08:00
aarch64-matmul.ll
aarch64-matrix-umull-smull.ll [AArch64] Reuse larger DUP if available 2022-05-29 19:42:13 +01:00
aarch64-minmaxv.ll
aarch64-mops-consecutive.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
aarch64-mops-mte.ll [AArch64] Do not use ABI alignment for mops.memset.tag 2022-02-01 14:37:53 +01:00
aarch64-mops.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
aarch64-mov-debug-locs.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-mull-masks.ll
aarch64-named-reg-w18.ll
aarch64-named-reg-x18.ll
aarch64-neon-v1i1-setcc.ll
aarch64-p2align-max-bytes-neoverse.ll [AArch64] Set MaxBytesForLoopAlignment for more targets 2022-03-31 11:37:11 +01:00
aarch64-p2align-max-bytes.ll [CodeGen] Emit alignment "Max Skip" operand 2022-01-05 12:54:30 +00:00
aarch64-sched-store.ll [test] Add test for D126700 NFC 2022-06-13 18:37:29 +08:00
aarch64-signedreturnaddress.ll
aarch64-smax-constantfold.ll
aarch64-smov-gen.ll [AArch64] Generate SMOV in place of sext(fmov(...)) 2021-08-25 15:23:22 +01:00
aarch64-smull.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
aarch64-split-and-bitmask-immediate.ll Third Recommit "[AArch64] Split bitmask immediate of bitwise AND operation" 2021-10-08 11:28:49 +01:00
aarch64-stp-cluster.ll
aarch64-sve-and-combine-crash.ll [AArch64ISelLowering] Fix null pointer access in performSVEAndCombine. 2021-09-10 10:36:43 -07:00
aarch64-sve-asm-negative.ll
aarch64-sve-asm.ll
aarch64-tail-dup-size.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
aarch64-tbz.ll
aarch64-tryBitfieldInsertOpFromOr-crash.ll
aarch64-unroll-and-jam.ll
aarch64-vcvtfp2fxs-combine.ll
aarch64-vector-pcs.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-vuzp.ll
aarch64-wide-mul.ll [AArch64] Common patterns between UMULL and int_aarch64_neon_umull 2022-02-19 14:38:57 +00:00
aarch64-wide-shuffle.ll [AArch64] Only mark cost 1 perfect shuffles as legal 2022-04-19 12:58:55 +01:00
aarch64_f16_be.ll
aarch64_tree_tests.ll
aarch64_win64cc_vararg.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
aarch64st1.mir [AArch64] Handle ST1iN instructions in isAArch64FrameOffsetLegal 2021-10-25 17:05:12 +03:00
active_lane_mask.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
adc.ll [AArch64] Add `foldADCToCINC` DAG combine. 2022-05-12 22:21:20 +01:00
add-negative.ll Allow bitwidth difference when checking for isOneOrOneSplat. 2022-06-16 16:04:20 +00:00
addcarry-crash.ll [AArch64] Add `foldADCToCINC` DAG combine. 2022-05-12 22:21:20 +01:00
addg_subg.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
addimm-mulimm.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
addr-of-ret-addr.ll
addrsig-macho.ll Implement support for __llvm_addrsig for MachO in llvm-mc 2022-05-03 18:19:18 -04:00
addsub-24bit-imm.mir [AArch64] Optimize add/sub with immediate through MIPeepholeOpt 2022-01-22 12:39:22 +00:00
addsub-constant-folding.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
addsub-shifted.ll
addsub.ll [AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt. 2022-02-19 15:35:53 +00:00
addsub_ext.ll [AArch64] Rewrite addsub_ext.ll test. NFC 2021-09-10 10:08:57 +01:00
align-down.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
alloca.ll
analyze-branch.ll
analyzecmp.ll
and-mask-removal.ll [TypePromotion] Extend TypePromotion::isSafeWrap 2021-11-14 11:18:31 +00:00
and-sink.ll
andandshift.ll [AArch64] Regenerate andandshift.ll test checks 2022-05-23 11:48:24 +01:00
andcompare.ll [AArch64] Genereate CCMP from And CSel 2022-02-02 13:48:16 +00:00
andorbrcompare.ll [AArch64] Attempt to emitConjunction from brcond 2022-02-08 11:27:10 +00:00
apple-latest-cpu.ll
argument-blocks-array-of-struct.ll [AArch64] Order STP Q's by ascending address 2022-05-23 09:50:44 +01:00
argument-blocks.ll
arm64-2011-03-09-CPSRSpill.ll
arm64-2011-03-17-AsmPrinterCrash.ll
arm64-2011-03-21-Unaligned-Frame-Index.ll
arm64-2011-04-21-CPSRBug.ll
arm64-2011-10-18-LdStOptBug.ll
arm64-2012-01-11-ComparisonDAGCrash.ll
arm64-2012-05-07-DAGCombineVectorExtract.ll
arm64-2012-05-07-MemcpyAlignBug.ll [InstCombine] handle subobjects of constant aggregates 2022-06-21 11:55:14 -06:00
arm64-2012-05-09-LOADgot-bug.ll
arm64-2012-05-22-LdStOptBug.ll
arm64-2012-06-06-FPToUI.ll
arm64-2012-07-11-InstrEmitterBug.ll
arm64-2013-01-13-ffast-fcmp.ll
arm64-2013-01-23-frem-crash.ll
arm64-2013-01-23-sext-crash.ll
arm64-2013-02-12-shufv8i8.ll
arm64-AdvSIMD-Scalar.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
arm64-AnInfiniteLoopInDAGCombine.ll
arm64-EXT-undef-mask.ll
arm64-aapcs-be.ll
arm64-aapcs.ll [AArch64] Emit AssertZExt for i1 arguments 2021-10-11 11:55:11 +03:00
arm64-abi-hfa-args.ll
arm64-abi-varargs.ll [DAGCombine] Add node in the worklist in topological order in CombineTo 2022-05-07 16:24:31 +00:00
arm64-abi.ll [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress 2021-08-02 14:48:44 -07:00
arm64-abi_align.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-addp.ll [AArch64] Generate ADDP from shuffled add 2022-06-06 11:39:51 +01:00
arm64-addr-mode-folding.ll
arm64-addr-type-promotion.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-addrmode.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-alloc-no-stack-realign.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-alloca-frame-pointer-offset.ll
arm64-andCmpBrToTBZ.ll Revert "[SimplifyCFG] Thread branches on same condition in more cases (PR54980)" 2022-07-05 16:57:46 +02:00
arm64-ands-bad-peephole.ll
arm64-anyregcc-crash.ll
arm64-anyregcc.ll
arm64-arith-saturating.ll
arm64-arith.ll
arm64-arm64-dead-def-elimination-flag.ll
arm64-assert-zext-sext.ll [AArch64] Remove redundant ORRWrs which is generated by zero-extend 2021-10-25 09:47:07 +01:00
arm64-atomic-128.ll [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`. 2022-05-12 22:17:23 +01:00
arm64-atomic.ll
arm64-bcc.ll
arm64-big-endian-bitconverts.ll
arm64-big-endian-eh.ll
arm64-big-endian-varargs.ll
arm64-big-endian-vector-callee.ll
arm64-big-endian-vector-caller.ll
arm64-big-imm-offsets.ll
arm64-big-stack.ll
arm64-bitfield-extract.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-blockaddress.ll
arm64-break.ll Reland "[COFF, ARM64] Add __break intrinsic" 2022-04-20 13:01:30 -07:00
arm64-build-vector.ll [AArch64] Known bits for AArch64ISD::DUP 2022-06-20 19:11:57 +01:00
arm64-builtins-linux.ll
arm64-call-tailcalls.ll
arm64-cast-opt.ll
arm64-ccmp-heuristics.ll
arm64-ccmp.ll Extend `performANDCSELCombine` to `performANDORCSELCombine` 2022-03-04 15:09:59 +00:00
arm64-clrsb.ll
arm64-coalesce-ext.ll
arm64-coalescing-MOVi32imm.ll
arm64-code-model-large-darwin.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-codegen-prepare-extload.ll
arm64-collect-loh-garbage-crash.ll
arm64-collect-loh-str.ll
arm64-collect-loh.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-complex-ret.ll
arm64-const-addr.ll
arm64-constrained-fcmp-no-nans-opt.ll
arm64-convert-v4f64.ll [AArch64] Add a tablegen pattern for UZP1. 2021-12-14 11:51:05 +00:00
arm64-copy-tuple.ll
arm64-crc32.ll [AArch64] Add support for the 'R' architecture profile. 2021-10-27 12:32:30 +01:00
arm64-crypto.ll
arm64-cse.ll [AArch64] Regenerate 3 codegen test files. NFC 2022-06-16 18:23:05 +01:00
arm64-csel.ll [DAGCombiner][AArch64] Enhance to support for scalar CSINC 2022-02-07 10:27:48 +08:00
arm64-csldst-mmo.ll
arm64-custom-call-saved-reg.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
arm64-cvt.ll
arm64-dagcombiner-convergence.ll
arm64-dagcombiner-dead-indexed-load.ll
arm64-dagcombiner-load-slicing.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-darwin-cc.ll
arm64-dead-def-frame-index.ll
arm64-dead-register-def-bug.ll
arm64-detect-vec-redux.ll
arm64-dup.ll [AArch64] Add Extract(DUP(C)) as a canonical constant. 2022-06-21 09:51:22 +01:00
arm64-early-ifcvt.ll
arm64-elf-calls.ll
arm64-elf-constpool.ll
arm64-ext.ll
arm64-extend-int-to-fp.ll
arm64-extend.ll
arm64-extload-knownzero.ll
arm64-extract.ll
arm64-extract_subvector.ll
arm64-fast-isel-addr-offset.ll
arm64-fast-isel-alloca.ll
arm64-fast-isel-br.ll
arm64-fast-isel-call.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-fast-isel-conversion-fallback.ll
arm64-fast-isel-conversion.ll
arm64-fast-isel-fcmp.ll
arm64-fast-isel-gv.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-fast-isel-icmp.ll
arm64-fast-isel-indirectbr.ll
arm64-fast-isel-intrinsic.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-fast-isel-materialize.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-fast-isel-noconvert.ll
arm64-fast-isel-rem.ll
arm64-fast-isel-ret.ll
arm64-fast-isel-store.ll
arm64-fast-isel.ll
arm64-fastcc-tailcall.ll
arm64-fastisel-gep-promote-before-add.ll
arm64-fcmp-opt.ll
arm64-fcopysign.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
arm64-fixed-point-scalar-cvt-dagcombine.ll [AArch64] Fix assumptions on input type of tryCombineFixedPointConvert 2022-05-23 08:55:54 +01:00
arm64-fma-combine-with-fpfusion.ll
arm64-fma-combines.ll [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant 2021-11-09 15:30:19 +03:00
arm64-fmadd.ll [AArch64] Add instruction selection for strict FP 2022-02-17 13:11:54 +00:00
arm64-fmax-safe.ll
arm64-fmax.ll
arm64-fminv.ll
arm64-fml-combines.ll
arm64-fmuladd.ll
arm64-fold-address.ll
arm64-fold-lsl.ll
arm64-fp-contract-zero.ll
arm64-fp-imm-size.ll
arm64-fp-imm.ll
arm64-fp.ll
arm64-fp128-folding.ll
arm64-fp128.ll [AArch64] Async unwind - Adjust unwind info in AArch64LoadStoreOptimizer 2022-04-18 12:09:44 +01:00
arm64-fpcr.ll
arm64-frame-index.ll
arm64-global-address.ll
arm64-hello.ll
arm64-homogeneous-prolog-epilog-bad-outline.mir
arm64-homogeneous-prolog-epilog-frame-tail.ll
arm64-homogeneous-prolog-epilog-no-helper.ll [AArch64] Async unwind - do not schedule frame setup/destroy 2022-02-24 17:24:04 +00:00
arm64-homogeneous-prolog-epilog.ll [AArch64] Fix Local Deallocation for Homogeneous Prolog/Epilog 2021-07-25 10:51:11 -07:00
arm64-i16-subreg-extract.ll
arm64-icmp-opt.ll
arm64-indexed-memory.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-indexed-vector-ldst-2.ll
arm64-indexed-vector-ldst.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-inline-asm-error-I.ll
arm64-inline-asm-error-J.ll
arm64-inline-asm-error-K.ll
arm64-inline-asm-error-L.ll
arm64-inline-asm-error-M.ll
arm64-inline-asm-error-N.ll
arm64-inline-asm-zero-reg-error.ll
arm64-inline-asm.ll [NFCI] Fixed missing colon in CHECK directives - part 2 2022-04-03 14:42:59 +02:00
arm64-instruction-mix-remarks.ll [AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt. 2022-02-19 15:35:53 +00:00
arm64-isel-or.ll [AArch64ISelDAGToDAG] Fix ORRWrs/ORRXrs usefulbits calculation bug 2021-07-06 00:38:42 +08:00
arm64-join-reserved.ll
arm64-jumptable.ll
arm64-large-frame.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
arm64-ld-from-st.ll
arm64-ld1.ll
arm64-ldp-aa.ll
arm64-ldp-cluster.ll
arm64-ldp.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-ldst-unscaled-pre-post.mir
arm64-ldur.ll
arm64-ldxr-stxr.ll [OpaquePtr][AArch64] Use elementtype on ldxr/stxr 2022-03-14 10:09:59 -07:00
arm64-leaf.ll
arm64-long-shift.ll
arm64-memcpy-inline.ll
arm64-memset-inline.ll [AArch64] Order STP Q's by ascending address 2022-05-23 09:50:44 +01:00
arm64-memset-to-bzero-pgso.ll
arm64-memset-to-bzero.ll [SelectionDAG] Handle bzero/memset libcalls globally instead of per target 2022-06-09 08:34:55 +00:00
arm64-misaligned-memcpy-inline.ll [AArch64] Regenerate some test checks. NFC 2021-09-12 12:13:29 +01:00
arm64-misched-basic-A53.ll
arm64-misched-basic-A57.ll
arm64-misched-forwarding-A53.ll
arm64-misched-memdep-bug.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
arm64-misched-multimmo.ll
arm64-movi.ll
arm64-mte.ll
arm64-mul.ll [AArch64] Regenerate arm64-mul.ll test checks 2022-07-16 15:27:47 +01:00
arm64-named-reg-alloc.ll
arm64-named-reg-notareg.ll
arm64-narrow-st-merge.ll
arm64-neg.ll
arm64-neon-2velem-high.ll [AArch64] Add extra widening mul tests. NFC 2022-02-17 19:11:45 +00:00
arm64-neon-2velem.ll
arm64-neon-3vdiff.ll [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
arm64-neon-aba-abd.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-neon-across.ll
arm64-neon-add-pairwise.ll
arm64-neon-add-sub.ll
arm64-neon-copy.ll [DAG] visitINSERT_VECTOR_ELT - attempt to reconstruct BUILD_VECTOR before other fold interfere 2022-06-13 11:48:18 +01:00
arm64-neon-copyPhysReg-tuple.ll
arm64-neon-mul-div-cte.ll
arm64-neon-mul-div.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
arm64-neon-scalar-by-elem-mul.ll
arm64-neon-select_cc.ll
arm64-neon-simd-ldst-one.ll [AArch64] Regenerate arm64-neon-simd-ldst-one.ll test checks 2022-07-16 15:27:47 +01:00
arm64-neon-simd-shift.ll
arm64-neon-simd-vget.ll
arm64-neon-v1i1-setcc.ll
arm64-neon-v8.1a.ll [ARM][AArch64] Introduce qrdmlah and qrdmlsh intrinsics 2022-01-27 19:19:46 +00:00
arm64-neon-vector-list-spill.ll
arm64-neon-vector-shuffle-extract.ll
arm64-nvcast.ll [AArch64] Add missing NVCAST patterns. 2022-05-07 21:08:14 +01:00
arm64-opt-remarks-lazy-bfi.ll [CodeGen] Async unwind - add a pass to fix CFI information 2022-04-11 13:27:26 +01:00
arm64-patchpoint-scratch-regs.ll
arm64-patchpoint-webkit_jscc.ll
arm64-patchpoint.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
arm64-pic-local-symbol.ll
arm64-platform-reg.ll
arm64-popcnt.ll [AArch64] Remove isDef32 2022-06-07 18:57:59 +01:00
arm64-prefetch.ll
arm64-preserve-most.ll
arm64-promote-const-complex-initializers.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-promote-const.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-raddhn-combine.ll [AArch64] Add a tablegen pattern for RADDHN/RADDHN2. 2021-12-24 11:13:25 +00:00
arm64-redzone.ll
arm64-reg-copy-noneon.ll
arm64-register-offset-addressing.ll
arm64-register-pairing.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-regress-f128csel-flags.ll
arm64-regress-interphase-shift.ll
arm64-regress-opt-cmp.mir
arm64-reserve-call-saved-reg.ll
arm64-reserved-arg-reg-call-error.ll
arm64-return-vector.ll
arm64-returnaddr.ll
arm64-rev.ll [DAGCombiner] Fix bug in MatchBSwapHWordLow. 2022-05-18 09:23:18 -07:00
arm64-rounding.ll
arm64-scaled_iv.ll
arm64-scvt.ll [AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32 2022-05-16 18:00:30 +01:00
arm64-setcc-int-to-fp-combine.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-shifted-sext.ll [AArch64] Remove isDef32 2022-06-07 18:57:59 +01:00
arm64-shrink-v1i64.ll
arm64-shrink-wrapping.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
arm64-simd-scalar-to-vector.ll
arm64-simplest-elf.ll
arm64-sincos.ll
arm64-sitofp-combine-chains.ll
arm64-sli-sri-opt.ll [AArch64] Known bits for AArch64ISD::DUP 2022-06-20 19:11:57 +01:00
arm64-smaxv.ll
arm64-sminv.ll
arm64-spill-lr.ll
arm64-spill-remarks-treshold-hotness.ll
arm64-spill-remarks.ll
arm64-spill.ll
arm64-sqshl-uqshl-i64Contant.ll
arm64-sqxtn2-combine.ll [AArch64] Add a tablegen pattern for SQXTN2. 2021-12-23 15:19:13 +00:00
arm64-srl-and.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-st1.ll
arm64-stack-no-frame.ll
arm64-stackmap-nops.ll
arm64-stackmap.ll Test stackmap support for floating point types. 2022-05-30 10:49:32 +01:00
arm64-stackpointer.ll
arm64-stacksave.ll
arm64-storebytesmerge.ll
arm64-stp-aa.ll
arm64-stp.ll
arm64-strict-align.ll
arm64-stur.ll
arm64-subsections.ll
arm64-subvector-extend.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
arm64-summary-remarks.ll
arm64-swizzle-tbl-i16-layout.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-tbl.ll
arm64-this-return.ll
arm64-tls-darwin.ll
arm64-tls-dynamic-together.ll
arm64-tls-dynamics.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-tls-initial-exec.ll
arm64-tls-local-exec.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-trap.ll [GlobalISel] Implement support for the "trap-func-name" attribute. 2021-09-20 14:32:01 -07:00
arm64-triv-disjoint-mem-access.ll
arm64-trn.ll [ARM][AArch64] Add some extra shuffle conversion test coverage. NFC 2022-05-05 15:27:44 +01:00
arm64-trunc-store.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-umaxv.ll
arm64-uminv.ll
arm64-umov.ll
arm64-unaligned_ldst.ll
arm64-uzp.ll
arm64-vaargs.ll
arm64-vabs.ll [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`. 2022-05-12 22:17:23 +01:00
arm64-vadd.ll
arm64-vaddlv.ll
arm64-vaddv.ll
arm64-variadic-aapcs.ll
arm64-vbitwise.ll
arm64-vclz.ll
arm64-vcmp.ll
arm64-vcnt.ll
arm64-vcombine.ll
arm64-vcvt.ll
arm64-vcvt_f.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
arm64-vcvt_f32_su32.ll
arm64-vcvt_n.ll
arm64-vcvt_su32_f32.ll
arm64-vcvtxd_f32_f64.ll
arm64-vecCmpBr.ll
arm64-vecFold.ll
arm64-vector-ext.ll
arm64-vector-imm.ll
arm64-vector-insertion.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
arm64-vector-ldst.ll [AArch64] Regenerate arm64-vector-ldst.ll test checks 2022-07-16 15:27:47 +01:00
arm64-vext.ll
arm64-vext_reverse.ll
arm64-vfloatintrinsics.ll
arm64-vhadd.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
arm64-vhsub.ll
arm64-virtual_base.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
arm64-vmax.ll [AArch64] Regenerate arm64-vmax.ll test checks 2022-07-16 15:27:47 +01:00
arm64-vminmaxnm.ll
arm64-vmovn.ll
arm64-vmul.ll [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
arm64-volatile.ll
arm64-vpopcnt.ll
arm64-vqadd.ll
arm64-vqsub.ll
arm64-vselect.ll [AArch64] Regenerate arm64-vselect.ll test checks 2022-07-13 13:52:15 +01:00
arm64-vsetcc_fp.ll
arm64-vshift.ll Recommit "[AArch64] Custom lower <4 x i8> loads" 2021-06-30 09:18:06 +01:00
arm64-vshr.ll [AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0) 2021-12-14 16:03:02 +00:00
arm64-vshuffle.ll [AArch64] Regenerate arm64-vshuffle.ll test checks 2022-07-13 13:52:15 +01:00
arm64-vsqrt.ll
arm64-vsra.ll
arm64-vsub.ll
arm64-weak-reference.ll
arm64-windows-calls.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64-windows-tailcall.ll
arm64-xaluo.ll AArch64/GlobalISel: Stop using legal s1 values 2022-07-08 11:55:08 -04:00
arm64-zero-cycle-regmov.ll
arm64-zero-cycle-zeroing.ll [CodeGen][AArch64] Fix typo in arm64-zero-cycle-zeroing.ll 2022-02-01 12:08:06 +00:00
arm64-zeroreg.ll
arm64-zext.ll
arm64-zextload-unscaled.ll
arm64-zip.ll
arm64_32-addrs.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
arm64_32-atomics.ll [OpaquePtr][AArch64] Use elementtype on ldxr/stxr 2022-03-14 10:09:59 -07:00
arm64_32-fastisel.ll
arm64_32-frame-pointers.ll
arm64_32-gep-sink.ll
arm64_32-memcpy.ll
arm64_32-neon.ll
arm64_32-null.ll
arm64_32-pointer-extend.ll
arm64_32-stack-pointers.ll
arm64_32-tls.ll
arm64_32-va.ll
arm64_32.ll [SelectionDAG] Handle bzero/memset libcalls globally instead of per target 2022-06-09 08:34:55 +00:00
asm-large-immediate.ll
asm-print-comments.ll
asm-srcloc.ll
assertion-rc-mismatch.ll
atomic-ops-ldapr.ll [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
atomic-ops-lse.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
atomic-ops-not-barriers.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
atomic-ops.ll [AArch64] Enable type promotion for AArch64 2021-09-29 15:13:12 +01:00
atomicrmw-O0.ll [fastregalloc] Enhance the heuristics for liveout in self loop. 2022-06-21 09:18:49 +08:00
atomicrmw-xchg-fp.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
autoupgrade-aarch64-neon-addp-float.ll
basic-pic.ll
bcax.ll Teach the AArch64 backend to instruction select the BCAX instruction. 2022-02-23 15:59:40 -08:00
bcmp-inline-small.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
bf16-convert-intrinsics.ll
bf16-vector-bitcast.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
bf16-vector-shuffle.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
bf16.ll [AArch64] Add isel for bitcasting between bfloat and half types. 2022-01-29 11:26:13 +00:00
bfis-in-loop.ll [TypePromotion] Avoid some unnecessary truncs 2022-05-13 09:45:20 +01:00
bics.ll
big-callframe.ll
bisect-post-ra-machine-sink.mir
bitcast-promote-widen.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
bitcast-v2i8.ll
bitcast.ll
bitfield-extract.ll
bitfield-insert-0.ll
bitfield-insert.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
bitfield.ll AArch64: clamp UBFX high-bit to 32-bits 2022-02-23 12:48:39 +00:00
bitreverse.ll
blockaddress.ll
bool-ext-inc.ll
bool-loads.ll
br-cond-not-merge.ll
br-to-eh-lpad.ll
br-undef-cond.ll
branch-folder-merge-mmos.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
branch-folder-oneinst.mir
branch-relax-alignment.ll Revert "Revert "Temporarily do not drop volatile stores before unreachable"" 2021-07-09 11:44:34 -04:00
branch-relax-asm.ll
branch-relax-bcc.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
branch-relax-block-size.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
branch-relax-cbz.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
branch-target-enforcement-indirect-calls.ll
branch-target-enforcement.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
breg.ll
bswap-known-bits.ll [SDAG] add demanded bits transform for bswap 2022-01-17 18:25:42 -05:00
bti-branch-relaxation.ll
build-one-lane.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
build-pair-isel.ll
build-vector-extract.ll [DAG] Canonicalize non-inlane shuffle -> AND if all non-inlane referenced elements are known zero 2022-07-16 11:38:24 +01:00
byval-type.ll
call-rv-marker.ll [AArch64] Cleanup call-rv-marker.ll test. NFC. 2022-04-12 10:34:54 -07:00
callbr-asm-label.ll [IR] Don't use blockaddresses as callbr arguments 2022-07-15 10:18:17 +02:00
callbr-asm-obj-file.ll [IR] Don't use blockaddresses as callbr arguments 2022-07-15 10:18:17 +02:00
callee-save.ll
ccmp-successor-probs.mir
cfguard-checks.ll
cfguard-module-flag.ll
cfi-fixup.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
cfi-fixup.mir [CodeGen] Async unwind - add a pass to fix CFI information 2022-04-11 13:27:26 +01:00
cfi_restore.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cfinv-def-nzcv.mir
cfinv-use-nzcv.mir
cgp-trivial-phi-node.ll
cgp-usubo.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
check-sign-bit-before-extension.ll Revert "[SimplifyCFG] Start redesigning `FoldTwoEntryPHINode()`." 2022-02-03 12:32:50 +03:00
chkstk.ll
clang-section-macho.ll [MC] Allow annotating custom sections as zerofill 2022-06-28 15:08:47 +01:00
cls.ll
cluster-frame-index.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cmp-bool.ll
cmp-chains.ll Extend `performANDCSELCombine` to `performANDORCSELCombine` 2022-03-04 15:09:59 +00:00
cmp-const-max.ll
cmp-frameindex.ll [Test] Regenerate some of llc test checks using auto updater 2021-10-28 16:18:30 +07:00
cmp-select-sign.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
cmp-to-cmn.ll Fix typo of colon to semicolon in lit tests 2021-10-09 10:03:50 +08:00
cmpwithshort.ll
cmpxchg-O0.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
cmpxchg-idioms.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
cmpxchg-lse-even-regs.ll
code-model-large-abs.ll
code-model-tiny-abs.ll
combine-and-like.ll
combine-andintoload.ll Revert "[DAG] Extend SearchForAndLoads with any_extend handling" 2022-02-01 20:18:40 +00:00
combine-comparisons-by-cse.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
combine-mul.ll [SDAG] try to fold one-demanded-bit-of-multiply 2022-02-07 17:24:35 -05:00
compare-branch.ll
compiler-ident.ll
complex-copy-noneon.ll
complex-fp-to-int.ll
complex-int-to-fp.ll
concat-vector.ll [AArch64] NFC: Clarify and auto-generate some CodeGen tests. 2022-01-24 17:42:37 +00:00
concat_vector-scalar-combine.ll
concat_vector-truncate-combine.ll [DAG] foldConstantFPMath - fold vector splats as well as scalar constants 2021-12-17 15:19:26 +00:00
concat_vector-truncated-scalar-combine.ll
cond-br-tuning.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
cond-sel-value-prop.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
cond-sel.ll
const-shift-of-constmasked.ll
consthoist-gep.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
convertphitype.ll
copyprop.ll Give option to use isCopyInstr to determine which MI is 2022-05-26 18:43:16 +00:00
copyprop.mir Give option to use isCopyInstr to determine which MI is 2022-05-26 18:43:16 +00:00
cpus.ll [AArch64] Support for Ampere1 core 2022-05-03 15:54:02 +01:00
csel-zero-float.ll
csinc-cmp-removal.mir [AArch64] Fix comparison peephole opt with non-0/1 immediate (PR51476) 2021-08-15 12:35:52 +02:00
csr-split.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
ctpop-nonean.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
cvt-fp-int-fp.ll [AArch64] Allow strict opcodes in fp->int->fp patterns 2022-02-17 13:11:54 +00:00
cxx-tlscc.ll AArch64: don't claim to preserve registers used by prologue code 2022-01-10 12:27:04 +00:00
dag-ReplaceAllUsesOfValuesWith.ll [DAG] Fix in ReplaceAllUsesOfValuesWith 2022-02-17 14:29:59 +01:00
dag-combine-insert-subvector.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
dag-combine-invaraints.ll
dag-combine-lifetime-end-store-typesize.ll [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
dag-combine-mul-shl.ll
dag-combine-select.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
dag-combine-trunc-build-vec.ll [AArch64] Add a tablegen pattern for UZP1. 2021-12-14 11:51:05 +00:00
dag-numsignbits.ll [DAG] SimplifyDemandedBits - add DemandedElts handling to ISD::SIGN_EXTEND_INREG simplification 2022-06-19 15:35:29 +01:00
darwinpcs-tail.ll [AArch64] Use correct calling convention for each vararg 2022-03-10 15:07:25 -08:00
dbg-declare-tag-offset.ll
dbg-value-tag-offset.ll
debug-info-sve-dbg-declare.mir Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
debug-info-sve-dbg-value.mir
debugtrap.ll [GlobalISel] Implement support for the "trap-func-name" attribute. 2021-09-20 14:32:01 -07:00
directcond.ll
div-rem-pair-recomposition-signed.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
div-rem-pair-recomposition-unsigned.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
div_minsize.ll [AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0) 2021-12-14 16:03:02 +00:00
divrem.ll
dllexport.ll
dllimport.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
dont-shrink-wrap-stack-mayloadorstore.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
dont-take-over-the-world.ll
dp-3source.ll
dp1.ll [AArch64] Remove isDef32 2022-06-07 18:57:59 +01:00
dp2.ll
dwarf-cfi.ll
early-ifcvt-regclass-mismatch.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
early-ifcvt-same-value.mir
eh_recoverfp.ll
ehcontguard.ll [MC] Make MCAsmInfo::isAcceptableChar reflect MCAsmInfo::doesAllowAtInName 2022-03-29 14:01:32 -07:00
elf-globals-pic.ll
elf-globals-static.ll
elf-preemption.ll
elim-dead-mi.mir [Aarch64] Correct register class for pseudo instructions 2021-09-09 14:31:49 -04:00
eliminate-trunc.ll
emutls.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
emutls_generic.ll
eon.ll
eor3.ll Teach the AArch64 backend patterns to generate the EOR3 instruction. 2021-08-30 20:01:08 +00:00
expand-blr-rvmarker-pseudo.mir llvm-reduce: Don't assert on functions which don't track liveness 2022-06-07 10:00:25 -04:00
expand-movi-renamable.mir
expand-select.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
expand-subs-pseudo.mir [AArch64] Avoid adding duplicate implicit operands when expanding pseudo insts. 2021-09-07 17:11:58 +08:00
expand-vector-rot.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
ext-narrow-index.ll [AArch64] NFC: Clarify and auto-generate some CodeGen tests. 2022-01-24 17:42:37 +00:00
extern-weak.ll
extra-callee-save.mir
extract-bits.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
extract-insert.ll
extract-lowbits.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
extract-sext-zext.ll [AArch64][Global ISel] Add sext/zext of vector extract improvements 2021-09-07 21:17:51 +01:00
extract.ll
f16-convert.ll
f16-imm.ll [AArch64] Regenerate some test checks. NFC 2021-09-08 11:08:32 +01:00
f16-instructions.ll [AArch64] Move fp16 intrinsics tests to new file. NFC 2022-07-11 20:36:46 +01:00
f16-neon-intrinsics.ll [AArch64] Move fp16 intrinsics tests to new file. NFC 2022-07-11 20:36:46 +01:00
fabd-no-neon.ll [AArch64] Add missing HasNEON predicate in scalar FABD patterns 2022-04-13 09:30:11 +00:00
fabs.ll [AArch64] Use simd mov to materialize big fp constants 2022-03-04 11:34:20 -05:00
fadd-combines.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
faddp-half.ll [AArch64] Generate FADDP from shuffled fadd 2022-06-11 14:16:37 +01:00
faddp.ll [AArch64] Generate FADDP from shuffled fadd 2022-06-11 14:16:37 +01:00
falkor-hwpf-fix.ll
falkor-hwpf-fix.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
falkor-hwpf.ll
fast-isel-address-extends.ll
fast-isel-addressing-modes.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
fast-isel-assume.ll
fast-isel-atomic.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
fast-isel-branch-cond-mask.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
fast-isel-branch-cond-split.ll [CodeGen] Async unwind - add a pass to fix CFI information 2022-04-11 13:27:26 +01:00
fast-isel-branch-uncond-debug.ll
fast-isel-branch_weights.ll
fast-isel-call-return.ll
fast-isel-cbz.ll
fast-isel-cmp-branch.ll
fast-isel-cmp-vec.ll Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants" 2022-01-13 15:59:43 +00:00
fast-isel-cmpxchg.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
fast-isel-const-float.ll [AArch64][GlobalISel] Add new MOVI pattern for fp constants 2022-03-29 10:57:22 +08:00
fast-isel-dbg.ll
fast-isel-erase.ll
fast-isel-folded-shift.ll
fast-isel-folding.ll
fast-isel-fpimm.ll
fast-isel-gep.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
fast-isel-int-ext.ll
fast-isel-int-ext2.ll
fast-isel-int-ext3.ll
fast-isel-int-ext4.ll
fast-isel-int-ext5.ll
fast-isel-intrinsic.ll
fast-isel-logic-op.ll
fast-isel-memcpy.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
fast-isel-mul.ll
fast-isel-runtime-libcall.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
fast-isel-sdiv.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
fast-isel-select.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
fast-isel-shift.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
fast-isel-sp-adjust.ll
fast-isel-sqrt.ll
fast-isel-switch-phi.ll
fast-isel-tail-call.ll
fast-isel-tbz.ll
fast-isel-trunc.ll
fast-isel-vector-arithmetic.ll
fast-isel-vret.ll
fast-regalloc-empty-bb-with-liveins.mir
fastcc-reserved.ll
fastcc.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
fastisel-debugvalue-undef.ll
fcmp.ll
fcopysign.ll [AArch64] Async unwind - Adjust unwind info in AArch64LoadStoreOptimizer 2022-04-18 12:09:44 +01:00
fcsel-zero.ll
fcvt-fixed.ll [AArch64] Use simd mov to materialize big fp constants 2022-03-04 11:34:20 -05:00
fcvt-int.ll
fcvt_combine.ll [AArch64] Ensure fixed point fptoi_sat has correct saturation width 2022-03-29 10:12:44 +01:00
fdiv-combine.ll [DAGCombiner] Fix invalid size request in combineRepeatedFPDivisors 2022-01-28 17:01:08 +00:00
fdiv_combine.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
fence-singlethread.ll AArch64: support ISel for fence instructions 2022-05-16 12:01:18 +01:00
fjcvtzs.ll
fjcvtzs.mir
flags-multiuse.ll
float-conv-elim.ll [SDAG] fix miscompile when casting int->FP->int 2022-05-02 14:57:27 -04:00
floatdp_1source.ll [AArch64] Rewrite floatdp_1source.ll test. NFC 2021-09-08 23:00:34 +01:00
floatdp_2source.ll
fmov-imm-licm.ll
fold-constants.ll
fold-csel-cttz-and.ll [AArch64] Generate AND in place of CSEL for predicated CTTZ 2022-05-20 13:41:32 +01:00
fold-global-offsets.ll [AArch64] Split fuse-literals feature 2022-04-11 05:27:11 +00:00
fp-cond-sel.ll
fp-const-fold.ll
fp-dp3.ll
fp-intrinsics-fp16.ll [AArch64] Lowering and legalization of strict FP16 2022-04-14 16:51:22 +01:00
fp-intrinsics-vector.ll [AArch64] Add some missing strict FP vector lowering 2022-02-17 16:10:31 +00:00
fp-intrinsics.ll [AArch64] Lowering and legalization of strict FP16 2022-04-14 16:51:22 +01:00
fp16-fmla.ll
fp16-v4-instructions.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
fp16-v8-instructions.ll [AArch64] fp16-v8-instructions.ll - remove some old defunct CHECKS identified in D125604 2022-05-18 12:49:05 +01:00
fp16-v16-instructions.ll [AArch64] Regenerate fp16 tests. 2021-08-02 13:05:16 -07:00
fp16-vector-bitcast.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
fp16-vector-load-store.ll
fp16-vector-nvcast.ll
fp16-vector-shuffle.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
fp16_intrinsic_lane.ll [AArch64] Regenerate some test checks. NFC 2021-09-08 11:08:32 +01:00
fp16_intrinsic_scalar_1op.ll
fp16_intrinsic_scalar_2op.ll
fp16_intrinsic_scalar_3op.ll DAG: Fix incorrect folding of fmul -1 to fneg 2021-09-14 21:25:02 -04:00
fp16_intrinsic_vector_1op.ll
fp16_intrinsic_vector_2op.ll
fp16_intrinsic_vector_3op.ll
fp128-folding.ll
fpclamptosat.ll [DAG] Create fptoui.sat from clamped fptoui 2022-01-26 08:37:44 +00:00
fpclamptosat_vec.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
fpconv-vector-op-scalarize.ll
fpenv.ll
fpimm.ll [AArch64] Use simd mov to materialize big fp constants 2022-03-04 11:34:20 -05:00
fptosi-sat-scalar.ll [AArch64] Use simd mov to materialize big fp constants 2022-03-04 11:34:20 -05:00
fptosi-sat-vector.ll [AArch64] Lower 3 and 4 sources buildvectors to TBL 2022-03-26 21:10:43 +00:00
fptosi-strictfp.ll [AArch64] provide strictfp attributes in test file 2021-08-26 16:56:43 +01:00
fptoui-sat-scalar.ll [SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeNumSignBits. 2022-01-09 17:48:05 -08:00
fptoui-sat-vector.ll [AArch64] Lower 3 and 4 sources buildvectors to TBL 2022-03-26 21:10:43 +00:00
fptouint-i8-zext.ll
frameaddr.ll
framelayout-fp-csr.ll
framelayout-frame-record.mir [AArch64] Async unwind - do not schedule frame setup/destroy 2022-02-24 17:24:04 +00:00
framelayout-offset-immediate-change.mir
framelayout-scavengingslot.mir
framelayout-sve-basepointer.mir
framelayout-sve-calleesaves-fix.mir [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
framelayout-sve-fixed-width-access.mir [AArch64] Improve access to fixed-width object when stack has SVE. 2022-03-04 09:33:59 +00:00
framelayout-sve-scavengingslot.mir
framelayout-sve.mir llvm-reduce: Don't assert on functions which don't track liveness 2022-06-07 10:00:25 -04:00
framelayout-unaligned-fp.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
free-zext.ll
frintn.ll
ftrunc.ll
func-argpassing.ll
func-calls.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
funclet-local-stack-size.ll
funclet-match-add-sub-stack.ll
funcptr_cast.ll
function-info-noredzone-present.ll
function-subtarget-features.ll
funnel-shift-rot.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
funnel-shift.ll [SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift. 2022-05-06 09:26:30 -07:00
gep-nullptr.ll
ghc-cc.ll
global-alignment.ll
global-merge-1.ll
global-merge-2.ll
global-merge-3.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
global-merge-4.ll
global-merge-group-by-use.ll [AArch64] Regenerate more tests. NFC 2022-07-03 15:49:16 +01:00
global-merge-hidden-minsize.ll
global-merge-ignore-single-use-minsize.ll
global-merge-ignore-single-use.ll
global-merge-minsize.ll
global-merge.ll
got-abuse.ll
hadd-combine.ll [DAGCombine] Move AVG combine to SimplifyDemandBits 2022-02-15 10:17:02 +00:00
half.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
highextractbitcast.ll [AArch64] Mark smull and umull as commutative. 2022-06-13 09:24:15 +01:00
hints.ll
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
hoist-and-by-const-from-shl-in-eqcmp-zero.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
hwasan-check-memaccess.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
hwasan-prefer-fp.ll
i1-contents.ll [AArch64] Emit AssertZExt for i1 arguments 2021-10-11 11:55:11 +03:00
i128-align.ll
i128-fast-isel-fallback.ll
i128-math.ll [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`. 2022-05-12 22:17:23 +01:00
i128_volatile_load_store.ll [AArch64] Split fuse-literals feature 2022-04-11 05:27:11 +00:00
i256-math.ll [SelectionDAG] computeKnownBits / ComputeNumSignBits for the remaining overflow-aware nodes 2022-07-08 09:19:19 +01:00
iabs.ll
icmp-shift-opt.ll [AArch64] Add `foldADCToCINC` DAG combine. 2022-05-12 22:21:20 +01:00
ifcvt-select.ll
illegal-float-ops.ll
ilp32-tlsdesc.ll
ilp32-va.ll
immcost.ll
implicit-null-check.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
implicit-sret.ll
inc-of-add.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
init-array.ll
inline-asm-blockaddress.ll
inline-asm-clobber.ll
inline-asm-constraints-bad-sve.ll
inline-asm-constraints-badI.ll
inline-asm-constraints-badK.ll
inline-asm-constraints-badK2.ll
inline-asm-constraints-badL.ll
inline-asm-globaladdress.ll
inline-asm-i-constraint-i1.ll
inline-asm-multilevel-gep.ll
inlineasm-S-constraint.ll
inlineasm-X-allocation.ll
inlineasm-X-constraint.ll [SelectionDAG] treat X constrained labels as i for asm 2022-01-11 10:29:40 -08:00
inlineasm-illegal-type.ll
inlineasm-ldr-pseudo.ll
inlineasm-output-template.ll
insert-extend.ll [AArch64] Convert vector add(ext, ext) into ext(add(ext, ext)) 2022-06-24 10:04:28 +01:00
insert-subvector-res-legalization.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
insert-subvector.ll [AArch64] Move v4i8 concat load lowering to a combine. 2022-04-14 15:19:33 +01:00
int-to-fp-no-neon.ll [AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32 2022-05-16 18:00:30 +01:00
intrinsics-memory-barrier.ll
irg-nomem.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irg.ll
irg_sp_tagp.ll
isinf.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
jti-correct-datatype.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
jump-table-32.ll [AArch64] Split fuse-literals feature 2022-04-11 05:27:11 +00:00
jump-table-compress.mir
jump-table-duplicate.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
jump-table-exynos.ll
jump-table.ll
known-never-nan.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
lack-of-signed-truncation-check.ll [AArch64] Enable type promotion for AArch64 2021-09-29 15:13:12 +01:00
landingpad-ifcvt.ll
large-consts.ll
large-stack-cmp.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
large-stack.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
large_shift.ll
ldp-stp-scaled-unscaled-pairs.ll
ldradr.ll
ldrpre-ldr-merge.mir AArch64: don't form indexed paired ops if base reg overlaps operands. 2021-08-20 11:39:38 +01:00
ldst-miflags.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-nopreidx-sp-redzone.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-opt-aa.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-opt-after-block-placement.ll
ldst-opt-mte-with-dbg.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
ldst-opt-mte.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
ldst-opt-non-imm-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-opt-zr-clobber.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-opt.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
ldst-opt.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-paired-aliasing.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
ldst-regoffset.ll
ldst-unscaledimm.ll
ldst-unsignedimm.ll [AArch64] Rewrite ldst-unsignedimm.ll codegen test. 2021-09-24 09:08:59 +01:00
ldst-zero.ll
legalize-bug-bogus-cpu.ll
lit.local.cfg
literal_pools_float.ll
live-debugvalues-sve.mir Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
live-interval-analysis.mir
llrint-conv-fp16.ll
llrint-conv.ll
llround-conv-fp16.ll
llround-conv.ll
llvm-ir-to-intrinsic.ll [SVE] Extend isel pattern coverage for BIC. 2022-01-28 13:14:46 +00:00
llvm-masked-gather-legal-for-sve.ll
llvm-masked-scatter-legal-for-sve.ll
load-combine-big-endian.ll [SDAG] try to canonicalize logical shift after bswap 2022-03-30 09:29:32 -04:00
load-combine.ll [SDAG] try to canonicalize logical shift after bswap 2022-03-30 09:29:32 -04:00
load-store-forwarding.ll
local_vars.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
logic-reassociate.ll [SDAG] simplify bitwise logic with repeated operand 2022-03-13 11:12:30 -04:00
logic-shift.ll [SDAG] match rotate pattern with extra 'or' operation 2022-03-09 13:19:00 -05:00
logical-imm.ll
logical_shifted_reg.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
loh-adrp-add-ldr-clobber.mir
loh-use-between-adrp-add.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loh.mir [AArch64][LOH] Don't ignore regmasks in bundles by iterating over instrs. 2022-04-12 10:34:54 -07:00
loop-micro-op-buffer-size-t99.ll
loop-sink-limit.mir [MachineSink] replace MachineLoop with MachineCycle 2022-05-26 06:45:23 -04:00
loop-sink.mir [Aarch64] Correct register class for pseudo instructions 2021-09-09 14:31:49 -04:00
lower-ptrmask.ll
lower-range-metadata-func-call.ll
lowerMUL-newload.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
lrint-conv-fp16-win.ll
lrint-conv-fp16.ll
lrint-conv-win.ll
lrint-conv.ll
lround-conv-fp16-win.ll
lround-conv-fp16.ll
lround-conv-win.ll
lround-conv.ll
ls64-inline-asm.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
ls64-intrinsics.ll
machine-combiner-copy.ll [AArch64] Look through copy in MachineCombiner FMUL patterns. 2022-05-31 09:28:00 +01:00
machine-combiner-fmul-dup.mir [AArch64] Look through copy in MachineCombiner FMUL patterns. 2022-05-31 09:28:00 +01:00
machine-combiner-instr-fmf.mir [AArch64] Make machine combiner patterns preserve MIFlags 2022-02-03 11:58:59 +00:00
machine-combiner-madd.ll
machine-combiner-reassociate.mir [AArch64] Adjust machine-combiner-reassociate.mir test 2022-02-03 12:40:14 +00:00
machine-combiner-subadd.ll [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency 2022-06-28 21:42:51 +00:00
machine-combiner-subadd2.mir [AArch64] Update test case. 2022-06-29 01:37:56 +00:00
machine-combiner-transient.ll [MachineCombiner] Don't compute the latency of transient instructions 2022-07-14 17:08:14 +00:00
machine-combiner.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
machine-combiner.mir
machine-copy-prop.ll
machine-copy-remove.ll
machine-copy-remove.mir
machine-cp-clobbers.mir [AArch64][test] Replace -march with -mtriple for llc RUN lines 2022-05-31 22:39:43 -07:00
machine-dead-copy.mir
machine-licm-sink-instr.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
machine-outliner-2fixup-blr-terminator.mir
machine-outliner-all-stack.mir
machine-outliner-bad-adrp.mir
machine-outliner-bad-register.mir
machine-outliner-bti.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-outliner-calls.mir
machine-outliner-cfi-tail-some.mir
machine-outliner-cfi-tail.mir
machine-outliner-cfi.mir Fix interaction of CFI instructions with MachineOutliner. 2022-06-10 13:37:49 -07:00
machine-outliner-compatible-candidates.mir
machine-outliner-create-lr-livein.mir [MachineOutliner][AArch64] Ensure LR is live-in when inserting reg-save calls 2021-09-08 17:44:27 -07:00
machine-outliner-default.mir
machine-outliner-drop-stack.mir
machine-outliner-flags.ll
machine-outliner-function-annotate.mir
machine-outliner-inline-asm-adrp.mir
machine-outliner-iterative-2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-outliner-iterative.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-outliner-mapping-stats.mir [MachineOutliner] Add testcase for instruction mapping stats 2022-02-17 18:26:59 -08:00
machine-outliner-no-noreturn-no-stack.mir
machine-outliner-noredzone.ll
machine-outliner-noreturn-no-stack.mir
machine-outliner-noreturn-save-lr.mir
machine-outliner-ordering.mir
machine-outliner-outline-bti.ll
machine-outliner-patchable.ll [MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL 2021-12-13 13:24:29 -08:00
machine-outliner-regsave.mir
machine-outliner-remarks.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
machine-outliner-retaddr-sign-cfi.ll [AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions. 2022-04-22 13:25:57 +02:00
machine-outliner-retaddr-sign-diff-scope-same-key.ll
machine-outliner-retaddr-sign-non-leaf.ll
machine-outliner-retaddr-sign-regsave.mir [AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions. 2022-04-22 13:25:57 +02:00
machine-outliner-retaddr-sign-same-scope-diff-key.ll
machine-outliner-retaddr-sign-same-scope-same-key-a.ll
machine-outliner-retaddr-sign-same-scope-same-key-b.ll
machine-outliner-retaddr-sign-sp-mod.ll
machine-outliner-retaddr-sign-sp-mod.mir [AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions. 2022-04-22 13:25:57 +02:00
machine-outliner-retaddr-sign-subtarget.ll
machine-outliner-retaddr-sign-thunk.ll [AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions. 2022-04-22 13:25:57 +02:00
machine-outliner-retaddr-sign-v8-3.ll
machine-outliner-side-effect-2.mir Fix the side effect of outlined function when the register is implicit use and implicit-def in the same instruction. 2021-11-17 09:44:10 -08:00
machine-outliner-side-effect.mir Fix the side effect of outlined function when the register is implicit use and implicit-def in the same instruction. 2021-11-17 09:44:10 -08:00
machine-outliner-size-info.mir
machine-outliner-tail.ll
machine-outliner-throw.ll [AArch64] Split fuse-literals feature 2022-04-11 05:27:11 +00:00
machine-outliner-throw2.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
machine-outliner-thunk.ll [AArch64] Regenerate some test checks. NFC 2021-09-08 11:08:32 +01:00
machine-outliner-unsafe-stack-call.mir
machine-outliner.ll
machine-outliner.mir
machine-scheduler.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-sink-getmemoperandwithoffset.mir
machine-sink-kill-flags.ll [Test] Regenerate some of llc test checks using auto updater 2021-10-28 16:18:30 +07:00
machine-sink-zr.mir
machine-zero-copy-remove.mir
machine_cse.ll
machine_cse_illegal_hoist.ll
machine_cse_impdef_killflags.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
macho-global-symbols.ll
macho-trap.ll
macro-fusion-last.mir
macro-fusion.ll
madd-combiner.ll [AArch64] Canonicalize X*(Y+1) or X*(1-Y) to madd/msub 2021-11-08 16:49:31 +08:00
madd-lohi.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
mattr-all.ll [AArch64] Add target feature "all" 2022-06-30 10:37:58 -07:00
mature-mc-support.ll
max-jump-table.ll
memcpy-f128.ll
memcpy-scoped-aa.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
memset-inline.ll [clang] Add support for __builtin_memset_inline 2022-06-10 13:13:59 +00:00
memset-vs-memset-inline.ll [clang] Add support for __builtin_memset_inline 2022-06-10 13:13:59 +00:00
memset.ll Use v16i8 rather than v2i64 as the VT for memset expansion on AArch64. 2021-08-19 16:54:07 +00:00
memsize-remarks.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
merge-scoped-aa-store.ll [SelectionDAG] Re-calculate scoped AA metadata when merging stores. 2021-09-21 11:41:17 -04:00
merge-store-dependency.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
merge-store.ll
merge-trunc-store.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
mergestores_noimplicitfloat.ll
midpoint-int.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
min-jump-table.ll
min-max.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
mingw-refptr.ll
minmax-of-minmax.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
minmax.ll Allow bitwidth difference when checking for isOneOrOneSplat. 2022-06-16 16:04:20 +00:00
misched-fusion-addr-tune.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
misched-fusion-addr.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
misched-fusion-aes.ll [Driver][AArch64]Add driver support for neoverse-512tvb target 2021-10-28 09:08:40 +01:00
misched-fusion-arith-logic.mir
misched-fusion-crypto-eor.mir
misched-fusion-csel.ll
misched-fusion-lit.ll [AArch64] Make FeatureFuseAdrpAdd a tune feature 2022-06-30 10:32:38 -07:00
misched-fusion.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
misched-predicate-virtreg.mir Add "REQUIRES: asserts" to test misched-predicate-virtreg.mir which uses "-debug-only". 2022-02-18 01:48:58 -08:00
misched-stp.ll
mla_mls_merge.ll [AArch64] Prefer fmov over orr v.16b when copying f32/f64 2021-08-03 17:25:40 +01:00
mlicm-stack-write-check.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
movid-no-neon.ll [AArch64] Avoid emitting MOVID when NEON is disabled 2022-05-14 14:40:51 +00:00
movimm-wzr.mir
movw-consts.ll [AArch64] Regenerate some more tests 2021-10-06 10:38:22 +01:00
movw-shift-encoding.ll
mul-lohi.ll
mul_by_elt.ll
mul_pow2.ll [DAG] try to convert multiply to shift via demanded bits 2022-02-23 12:09:32 -05:00
multi-vector-store-size.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
named-vector-shuffle-reverse-neon.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
named-vector-shuffle-reverse-sve.ll [CodeGen][SVE] Add missing isel patterns for vector_reverse 2021-11-18 09:59:26 +00:00
named-vector-shuffles-neon.ll [IR] Change vector.splice intrinsic to reject out-of-bounds indices 2022-01-11 09:37:39 +00:00
named-vector-shuffles-sve.ll [AArch64] NFC: Clarify and auto-generate some CodeGen tests. 2022-01-24 17:42:37 +00:00
neg-abs.ll [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`. 2022-05-12 22:17:23 +01:00
neg-imm.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
neg-selects.ll [AARCH64][DAGCombine] Add combine for negation of CSEL absolute value pattern. 2022-02-22 09:59:36 +00:00
neon-abd.ll [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`. 2022-05-12 22:17:23 +01:00
neon-addlv.ll [AArch64] Expand UADDLV patterns to SADDLV 2022-02-04 14:07:02 +00:00
neon-bitcast.ll
neon-bitselect.ll
neon-bitwise-instructions.ll [DAG] Canonicalize non-inlane shuffle -> AND if all non-inlane referenced elements are known zero 2022-07-16 11:38:24 +01:00
neon-compare-instructions.ll
neon-diagnostics.ll
neon-dot-product.ll [AArch64] Support for Ampere1 core 2022-05-03 15:54:02 +01:00
neon-dotpattern.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
neon-dotreduce.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
neon-extadd.ll [AArch64] Convert vector add(ext, ext) into ext(add(ext, ext)) 2022-06-24 10:04:28 +01:00
neon-extract.ll
neon-extracttruncate.ll [AArch64] Lower 3 and 4 sources buildvectors to TBL 2022-03-26 21:10:43 +00:00
neon-fma-FMF.ll
neon-fma.ll
neon-fp16fml.ll
neon-fpextend_f16.ll
neon-fpround_f128.ll
neon-idiv.ll
neon-inline-asm-16-bit-fp.ll
neon-mla-mls.ll [MachineCombiner] Don't compute the latency of transient instructions 2022-07-14 17:08:14 +00:00
neon-mov.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
neon-or-combine.ll
neon-perm.ll [AArch64] Turn UZP1 with undef operand into truncate 2022-03-04 11:12:26 +00:00
neon-reverseshuffle.ll [AArch64] Only mark cost 1 perfect shuffles as legal 2022-04-19 12:58:55 +01:00
neon-sad.ll
neon-scalar-by-elem-fma.ll [AArch64] Allow strict opcodes in indexed fmul and fma patterns 2022-02-17 13:11:54 +00:00
neon-scalar-copy.ll
neon-sha3.ll
neon-shift-left-long.ll
neon-shift-neg.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
neon-sm4-sm3.ll
neon-stepvector.ll [AArch64] NFC: Clarify and auto-generate some CodeGen tests. 2022-01-24 17:42:37 +00:00
neon-truncstore.ll [AArch64] Add a tablegen pattern for UZP1. 2021-12-14 11:51:05 +00:00
neon-vcadd.ll
neon-vcmla.ll
neon-vmull-high-p8.ll [AARCH64][NEON] Allow to sink operands for aarch64_neon_pmull 2022-02-03 16:46:49 +00:00
neon-vmull-high-p64.ll [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
neon-wide-splat.ll [AArch64] Add lane moves to PerfectShuffle tables 2022-04-19 14:49:50 +01:00
neon-widen-shuffle.ll [AArch64] Only mark cost 1 perfect shuffles as legal 2022-04-19 12:58:55 +01:00
neon_rbit.ll
nest-register.ll
new-load-requires-renaming-in-mssa.ll [InterleavedLoadComb] Rename uses when inserting new uses. 2022-06-14 13:15:23 +01:00
no-fp-asm-clobbers-crash.ll
no-quad-ldp-stp.ll
no-stack-arg-probe.ll
no_cfi.ll
nomerge.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
nonlazybind.ll
nontemporal.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
note-gnu-property-pac-bti-0.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
note-gnu-property-pac-bti-1.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
note-gnu-property-pac-bti-2.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
note-gnu-property-pac-bti-3.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
note-gnu-property-pac-bti-4.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
nzcv-save.ll [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`. 2022-05-12 22:17:23 +01:00
optimize-cond-branch.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
optimize-imm.ll [AArch64] Regenerate optimize-imm.ll test checks 2022-07-15 13:54:17 +01:00
or-combine.ll
overeager_mla_fusing.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
overlapping-copy-bundle-cycle.mir
overlapping-copy-bundle.mir
pacbti-llvm-generated-funcs-1.ll
pacbti-llvm-generated-funcs-2.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-module-attrs.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
paired-load.ll
parity.ll
partial-pipeline-execution.ll
patchable-function-entry-bti.ll
patchable-function-entry-empty.mir
patchable-function-entry.ll
peephole-and-tst.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
peephole-opt-check-cflags.mir
peephole-orr.mir [AArch64] Remove ToBeRemoved from AArch64MIPeepholeOpt 2022-06-08 17:26:07 +01:00
phi-dbg.ll
pic-eh-stubs.ll
pie.ll
popcount.ll [AArch64][GlobalISel] Legalize ctpop s128 2021-08-05 11:54:53 -07:00
post-ra-machine-sink.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
postra-mi-sched.ll
pow.75.ll Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if" 2022-04-06 20:32:53 +03:00
pow.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
powi-windows.ll
powi.ll [SimplifyLibCalls] refactor pow(x, n) expansion where n is a constant integer value 2022-07-09 12:00:22 -04:00
pr27816.ll
pr33172.ll [NFC][Codegen] Tune a few tests to not end with a naked `unreachable` terminator 2021-07-02 23:33:30 +03:00
pr40091.ll
pr48188.ll [AArch64][GlobalISel] Widen G_PHI before clamping it during legalization 2021-08-04 10:25:14 -07:00
pr49781.ll
pr51476.ll [DAGCombine] Add node in the worklist in topological order in CombineTo 2022-05-07 16:24:31 +00:00
pr51516.mir Fix late rematerialization operands check 2021-08-23 12:23:58 -07:00
pr53315-returned-i128.ll [AArch64][GlobalISel] Support returned argument with multiple registers 2022-01-24 10:55:28 +01:00
pr55178.ll [SelectionDAG] Constant fold (sext_inreg undef, VT) to 0 instead of undef. 2022-05-05 09:45:35 -07:00
pr55201.ll [DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask. 2022-04-30 11:02:30 -07:00
pr55644.ll [DAGCombiner][AArch64] Don't fold (smulo x, 2) -> (saddo x, x) if VT is i2. 2022-05-23 11:13:57 -07:00
preferred-alignment.ll
preferred-function-alignment.ll [AArch64] Set MaxBytesForLoopAlignment for more targets 2022-03-31 11:37:11 +01:00
prefixdata.ll
preserve_mostcc.ll
print-mrs-system-register.ll
prologue-epilogue-remarks.mir
ptrauth-intrinsic-sign-generic.ll [AArch64][PAC] Select llvm.ptrauth.sign/sign.generic to PAC*. 2021-11-18 15:21:30 -08:00
ptrauth-intrinsic-sign.ll [AArch64][PAC] Select llvm.ptrauth.sign/sign.generic to PAC*. 2021-11-18 15:21:30 -08:00
pull-binop-through-shift.ll
pull-conditional-binop-through-shift.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
qmovn.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
ragreedy-csr.ll
ragreedy-local-interval-cost.ll [AArch64] Order STP Q's by ascending address 2022-05-23 09:50:44 +01:00
rand.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
rbit.ll
read-pc.ll
readcyclecounter.ll [AArch64] FeaturePerfMon Added to CPUs 2022-02-08 11:19:26 +00:00
recp-fastmath.ll
reduce-and.ll [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal 2022-07-07 09:33:54 +00:00
reduce-or.ll [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal 2022-07-07 09:33:54 +00:00
reduce-shuffle.ll [AArch64] Convert vector add(ext, ext) into ext(add(ext, ext)) 2022-06-24 10:04:28 +01:00
reduce-xor.ll [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal 2022-07-07 09:33:54 +00:00
redundant-copy-elim-empty-mbb.ll Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants" 2022-01-13 15:59:43 +00:00
redundant-mov-from-zero-extend.ll [AArch64] Remove redundant ORRWrs which is generated by zero-extend 2021-10-25 09:47:07 +01:00
redundant-orrwrs-from-zero-extend.mir [AArch64] Remove redundant ORRWrs which is generated by zero-extend 2021-10-25 09:47:07 +01:00
reg-scavenge-frame.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regalloc-last-chance-recolor-with-split.mir [Greedy RegAlloc] Fix the handling of split register in last chance re-coloring. 2022-06-14 12:04:17 +07:00
regcoal-physreg.mir
regress-bitcast-formals.ll
regress-combine-extract-vectors.ll
regress-f128csel-flags.ll
regress-fp128-livein.ll
regress-tail-livereg.ll
regress-tblgen-chains.ll [AArch64] Regenerate 3 codegen test files. NFC 2022-06-16 18:23:05 +01:00
regress-w29-reserved-with-fp.ll
relaxed-fp-atomics.ll [AArch64] Add patterns for relaxed atomic ld/st into fp registers 2022-01-25 15:33:37 +03:00
reloc-specifiers.mir
rem_crash.ll
remat-const-float-simd.ll [AArch64] Use simd mov to materialize big fp constants 2022-03-04 11:34:20 -05:00
remat-float0.ll
remat.ll [AArch64] Support for Ampere1 core 2022-05-03 15:54:02 +01:00
returnaddr.ll
reverse-csr-restore-seq.mir [AArch64] Async unwind - Always place the first LDP at the end when ReverseCSRRestoreSeq is true 2022-02-24 18:48:07 +00:00
rm_redundant_cmp.ll
rmif-def-nzcv.mir
rmif-use-nzcv.mir
rotate-extract.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
rotate.ll
round-conv.ll
round-fptosi-sat-scalar.ll
round-fptoui-sat-scalar.ll
rvmarker-pseudo-expansion-and-outlining.mir [ObjCARC] Require the function argument in the clang.arc.attachedcall bundle. 2022-01-28 12:41:45 -08:00
sadd_sat.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sadd_sat_plus.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sadd_sat_vec.ll [AArch64] Add `foldOverflowCheck` DAG combine 2022-04-21 14:56:38 +01:00
sat-add.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
scalable-vector-promotion.ll
sched-past-vector-ldst.ll
scheduledag-constreg.mir
sdag-no-typesize-warnings-regandsizes.ll
sdag-store-merging-bug.ll
sdivpow2.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
seh-finally.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
seh_funclet_x1.ll
select-constant-xor.ll [DAG] Fix GT -> GE condition when creating SetCC 2021-09-08 12:41:51 +01:00
select-with-and-or.ll Extend `performANDCSELCombine` to `performANDORCSELCombine` 2022-03-04 15:09:59 +00:00
select_cc.ll [AArch64] Bail out for float operands in SetCC optimization. 2022-01-31 18:20:47 +00:00
select_const.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
select_fmf.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
selectcc-to-shiftand.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
selectiondag-order.ll
semantic-interposition-asm.ll
seqpaircopy.mir
seqpairspill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
setcc-fsh.ll [SDAG] try to reduce compare of funnel shift equal 0 2022-04-11 07:44:58 -04:00
setcc-takes-i32.ll
setcc-type-mismatch.ll
setf8-def-nzcv.mir
setf8-use-nzcv.mir
setf16-def-nzcv.mir
setf16-use-nzcv.mir
setjmp-bti-no-enforcement.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
setjmp-bti-outliner.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
setjmp-bti.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
settag-merge-order.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
settag-merge.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
settag-merge.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
settag.ll [AArch64] Async unwind - Fix MTE codegen emitting frame adjustments in a loop 2022-04-15 14:00:23 +01:00
shadow-call-stack.ll [AArch64] Emit CFI instruction for updating x18 when using ShadowCallStack with exception unwinding 2021-10-08 14:20:26 -07:00
shift-accumulate.ll Optimize shift and accumulate pattern in AArch64. 2022-01-20 01:57:40 +00:00
shift-amount-mod.ll [AArch64] Add a special case for shifting by (BitWidth - 1) - X 2022-02-11 08:23:33 +00:00
shift-by-signext.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
shift-logic.ll
shift-mod.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
shift_minsize.ll [AArch64] NFC: Clarify and auto-generate some CodeGen tests. 2022-01-24 17:42:37 +00:00
shrink-constant-multiple-users.ll
shrink-wrap.ll
shrink-wrapping-vla.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
shuffle-mask-legal.ll
shuffle-tbl34.ll [AArch64] Teach perfect shuffles tables about D-lane movs 2022-05-17 18:16:45 +01:00
shuffles.ll [AArch64] Teach perfect shuffles tables about D-lane movs 2022-05-17 18:16:45 +01:00
sibling-call.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
sign-return-address-cfi-negate-ra-state.ll
sign-return-address.ll [AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions. 2022-04-22 13:25:57 +02:00
signbit-shift.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
signed-truncation-check.ll [AArch64] Enable type promotion for AArch64 2021-09-29 15:13:12 +01:00
simple-macho.ll
sincos-expansion.ll
sincospow-vector-expansion.ll
sink-addsub-of-const.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
sink-copy-for-shrink-wrap.ll
sinksplat.ll [AArch64] Cost all perfect shuffles entries as cost 1 2022-04-19 12:05:05 +01:00
sitofp-fixed-legal.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
sme-get-pstatesm.ll [AArch64][SME] Add some SME PSTATE setting/query intrinsics 2022-06-22 10:26:45 +01:00
sme-intrinsics-add.ll [AArch64][SME] Add SME addha/va intrinsics 2022-07-05 09:47:17 +01:00
sme-intrinsics-loads.ll [AArch64][SME] Update load/store intrinsics to take predicate corresponding to element size. 2022-07-07 07:39:27 +00:00
sme-intrinsics-mopa.ll [AArch64][SME] Add SME outer product intrinsics 2022-06-28 09:41:44 +01:00
sme-intrinsics-mops.ll [AArch64][SME] Add SME outer product intrinsics 2022-06-28 09:41:44 +01:00
sme-intrinsics-mova-extract.ll [AArch64][SME] Sink tile offset operands into the loop for load/store instructions. 2022-06-28 10:28:36 +01:00
sme-intrinsics-mova-insert.ll [AArch64][SME] Sink tile offset operands into the loop for load/store instructions. 2022-06-28 10:28:36 +01:00
sme-intrinsics-rdsvl.ll [AArch64][SME] Add SME cntsb/h/w/d intrinsics 2022-06-16 10:50:25 +01:00
sme-intrinsics-stores.ll [AArch64][SME] Update load/store intrinsics to take predicate corresponding to element size. 2022-07-07 07:39:27 +00:00
sme-intrinsics-zero.ll [AArch64][SME] Add the zero intrinsic 2022-06-20 14:27:59 +01:00
sme-read-write-tpidr2.ll [AArch64][SME] Add some SME PSTATE setting/query intrinsics 2022-06-22 10:26:45 +01:00
space.ll
special-reg.ll
speculation-hardening-dagisel.ll
speculation-hardening-loads.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
speculation-hardening-sls-blr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
speculation-hardening-sls.ll [IR] Don't use blockaddresses as callbr arguments 2022-07-15 10:18:17 +02:00
speculation-hardening-sls.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
speculation-hardening.ll
speculation-hardening.mir [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
spill-fold.ll
spill-fold.mir [AARCH64 folding] Do not fold any copy with NZCV 2022-06-21 10:38:49 +07:00
spill-stack-realignment.mir
spill-undef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spillfill-sve.ll Fix the default alignment of i1 vectors. 2021-07-31 14:09:59 -07:00
spillfill-sve.mir
split-vector-insert.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sponentry.ll
sqrt-fastmath.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
srem-lkk.ll [AArch64][SelectionDAG] stick all the power-of-two tests in a separate file; NFC 2022-04-14 00:48:28 +08:00
srem-pow2.ll [Arch64][SelectionDAG] Add target-specific implementation of srem 2022-04-19 02:49:42 +08:00
srem-seteq-illegal-types.ll [ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4. 2022-06-02 00:49:11 +00:00
srem-seteq-optsize.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
srem-seteq-vec-nonsplat.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
srem-seteq-vec-splat.ll [SDAG] fold sub-of-shift to add-of-shift 2022-02-18 11:55:50 -05:00
srem-seteq.ll [Arch64][SelectionDAG] Add target-specific implementation of srem 2022-04-19 02:49:42 +08:00
srem-vector-lkk.ll [Arch64][SelectionDAG] Add target-specific implementation of srem 2022-04-19 02:49:42 +08:00
sshl_sat.ll [DAGCombiner] Fold SSHLSAT/USHLSAT to SHL when no saturation will occur 2022-02-06 18:59:06 +01:00
ssub_sat.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
ssub_sat_plus.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
ssub_sat_vec.ll [AArch64] Add `foldOverflowCheck` DAG combine 2022-04-21 14:56:38 +01:00
stack-guard-reassign-sve.mir [AArch64][SVE] Fix handling of stack protection with SVE 2021-12-14 11:30:48 +00:00
stack-guard-reassign.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
stack-guard-reassign.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stack-guard-remat-bitcast.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
stack-guard-sve.ll [AArch64] Improve access to fixed-width object when stack has SVE. 2022-03-04 09:33:59 +00:00
stack-guard-sysreg.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
stack-guard-vaarg.ll
stack-id-pei-alloc.mir
stack-id-stackslot-scavenging.mir
stack-protector-musttail.ll
stack-protector-target.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
stack-tagging-cfi.ll [MC] Add 'G' to augmentation string for MTE instrumented functions 2022-06-08 12:36:32 -07:00
stack-tagging-dbg.ll [DebugInfo] Correctly update dbg.values with duplicated location ops 2021-07-14 11:17:24 +01:00
stack-tagging-ex-1.ll
stack-tagging-ex-2.ll
stack-tagging-initializer-merge.ll
stack-tagging-loop.ll [MTE] [HWASan] Use LoopInfo for reachability queries. 2022-06-22 15:28:49 -07:00
stack-tagging-musttail.ll [mte] fix compiler crash with musttail. 2022-02-02 16:13:46 -08:00
stack-tagging-setjmp.ll [mte] work around lifetime issue with setjmp. 2022-02-02 13:55:09 -08:00
stack-tagging-split-lifetime.ll [MTE] [HWASan] Support diamond lifetimes. 2022-06-22 11:16:34 -07:00
stack-tagging-stack-coloring.ll [MTE] Add test that stack tagging does not mess up stack coloring. 2022-03-14 13:36:21 -07:00
stack-tagging-unchecked-ld-st.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
stack-tagging-untag-placement.ll
stack-tagging.ll
stack_guard_remat.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
stackguard-internal.ll
stackmap-dynamic-alloca.ll [STACKMAPS] Document+test UINT64_MAX stack size. 2022-06-27 11:57:07 +01:00
stackmap-frame-setup.ll
stackmap-liveness.ll
stackmap.ll [stackmaps] Legalise patchpoint arguments. 2022-07-15 12:01:59 +01:00
statepoint-call-lowering-lr.ll [STATEPOINT] Mark LR is early-clobber implicit def. 2022-02-21 10:37:43 +07:00
statepoint-call-lowering-sp.ll [Statepoint] Update gc.statepoint calls in tests with elementtype (NFC) 2022-02-04 14:15:41 +01:00
statepoint-call-lowering.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
stgp.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
store_merge_pair_offset.ll
storepairsuppress_minsize.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
stp-opt-with-renaming-debug.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stp-opt-with-renaming-ld3.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stp-opt-with-renaming-reserved-regs.mir [AArch64][SME] Add load and store instructions 2021-07-16 10:11:10 +00:00
stp-opt-with-renaming-undef-assert.mir [IR] Enable opaque pointers by default 2022-06-02 09:40:56 +02:00
stp-opt-with-renaming.mir MachineVerifier: Diagnose undef set on full register defs 2022-04-05 22:19:17 -04:00
strict-fp-int-promote.ll
strict-fp-opt.ll [AArch64] Add mayRaiseFPException to appropriate instructions 2022-04-14 16:51:22 +01:00
strpre-str-merge.mir AArch64: don't form indexed paired ops if base reg overlaps operands. 2021-08-20 11:39:38 +01:00
strqro.ll
strqu.ll [AArch64] Regenerate some test checks. NFC 2021-09-08 11:08:32 +01:00
sub-of-bias.ll
sub-of-not.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
sub-splat-sub.ll [DAG] Fold neg(splat(neg(x)) -> splat(x) 2021-06-25 19:53:29 +01:00
sub1.ll [SDAG] enhance sub->xor fold to ignore signbit 2022-07-11 12:37:50 -04:00
subs-to-sub-opt.ll
sve-aba.ll [SVE] Lower "unpredicated" sabd/uabd intrinsics to ISD::ABDS/U. 2022-06-22 00:02:51 +01:00
sve-abd.ll [DAGCombiner] Extend ISD::ABDS/U combine to handle more cases. 2022-02-17 13:32:20 +00:00
sve-adr.ll [AArch64][SVE] Add patterns to generate ADR instruction 2021-09-21 15:50:49 -07:00
sve-alloca-stackid.ll
sve-alloca.ll [AArch64][SVE] Restore SP from FP when SVE CSRs and variable sized objects are present 2022-05-04 12:57:03 +00:00
sve-bad-intrinsics.ll
sve-bad-select.ll
sve-bit-counting-pred.ll
sve-bit-counting.ll
sve-bitcast.ll [SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST. 2022-06-11 10:41:13 +01:00
sve-breakdown-scalable-vectortype.ll [AArch64][SelectionDAG] Support passing/returning scalable vectors with unusual types. 2021-08-02 15:53:16 -07:00
sve-callbyref-notailcall.ll
sve-calling-convention-byref.ll Fix the default alignment of i1 vectors. 2021-07-31 14:09:59 -07:00
sve-calling-convention-mixed.ll [SVE][AArch64] Refine hasSVEArgsOrReturn 2022-07-01 13:24:55 +00:00
sve-calling-convention-tuple-types.ll
sve-calling-convention.ll
sve-cmp-folds.ll [NFC][SVE] Add tests for zext(cmpeq(x, splat(0))) 2022-07-14 09:32:20 +00:00
sve-cmp-select.ll [AArch64][SVE] Fold away SETCC if original input was predicate vector. 2022-02-28 14:12:43 +00:00
sve-cntp-combine.ll [SVE] Extend isel pattern coverage for INCP & DECP. 2022-01-31 19:05:05 +00:00
sve-coalesce-ptrue-intrinsics.ll
sve-copy-zprpair.mir
sve-expand-div.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-extract-element.ll [AArch64] Enhance last active true vector combine 2022-04-06 09:54:28 +08:00
sve-extract-fixed-from-scalable-vector.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sve-extract-fixed-vector.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sve-extract-scalable-vector.ll [AArch64] Add support for insert/extract for nxv1i1 types. 2022-07-04 15:54:03 +00:00
sve-extract-subvector.ll
sve-extract-vector-to-predicate-store.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sve-fcmp.ll [SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an immediate. 2022-07-01 00:56:22 +01:00
sve-fcopysign.ll [AArch64][NEON][SVE] Lower FCOPYSIGN using AArch64ISD::BSP 2022-02-07 14:35:26 +00:00
sve-fcvt.ll [AArch64][SVE] Remove false register dependency for unary FP convert operations 2022-02-04 09:55:39 +00:00
sve-fix-length-and-combine-512.ll [AArch64] Regenerate more tests. NFC 2022-07-03 15:49:16 +01:00
sve-fixed-ld2-alloca.ll [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo 2022-02-17 17:09:17 +00:00
sve-fixed-length-bit-counting.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-bitcast.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-bitselect.ll Autogenerate sve-fixed-length-bitselect.ll . NFC 2022-06-12 01:53:05 +00:00
sve-fixed-length-concat.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-ext-loads.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-extract-subvector.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sve-fixed-length-extract-vector-elt.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-arith.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-compares.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-convert.ll [AArch64][SVE] Fix selection failure caused by fp/int convert using non-Neon types 2022-02-11 11:46:59 +00:00
sve-fixed-length-fp-extend-trunc.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-fma.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-minmax.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-reduce.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-rounding.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-select.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-to-int.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-fp-vselect.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-frame-offests-crash.ll Autogenerate sve-fixed-length-frame-offests-crash.ll . NFC 2022-06-12 01:54:10 +00:00
sve-fixed-length-frame-offests.ll [AArch64] Preserve chain when lowering fixed length load to SVE (PR55281) 2022-05-12 16:03:32 +02:00
sve-fixed-length-insert-vector-elt.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-arith.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-compares.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-div.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-extends.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-immediates.ll [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED. 2022-02-10 17:22:01 +00:00
sve-fixed-length-int-log.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-minmax.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-mulh.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-reduce.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-rem.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-select.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-shifts.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-to-fp.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-int-vselect.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-limit-duplane.ll [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED. 2022-02-10 17:22:01 +00:00
sve-fixed-length-loads.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-log-reduce.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-mask-opt.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-masked-gather.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-masked-loads.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-masked-scatter.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-masked-stores.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-no-vscale-range.ll [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal types 2022-03-11 09:57:58 +00:00
sve-fixed-length-optimize-ptrue.ll [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED. 2022-02-10 17:22:01 +00:00
sve-fixed-length-permute-rev.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-permute-zip-uzp-trn.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
sve-fixed-length-ptest.ll [SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an immediate. 2022-07-01 00:56:22 +01:00
sve-fixed-length-reshuffle.ll [SVE][CodeGen] Bail out for scalable vectors in AArch64TargetLowering::ReconstructShuffle 2022-02-10 14:18:49 +00:00
sve-fixed-length-rev.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-sdiv-pow2.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-shuffles.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-splat-vector.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-stores.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-subvector.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-trunc-stores.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-trunc.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fixed-length-vector-shuffle.ll [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. 2022-06-17 00:30:56 +01:00
sve-fold-loadext-and-splat-vector.ll [DAGCombine] Support splat_vector nodes in (and (extload)) dagcombine 2022-05-16 11:25:20 +00:00
sve-fold-vscale.ll
sve-forward-st-to-ld.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-fp-combine.ll [SVE] Only combine (fneg (fma)) => FNMLA with nsz 2021-12-13 11:33:07 +00:00
sve-fp-immediates-merging.ll [SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR. 2022-06-22 00:11:24 +01:00
sve-fp-reciprocal.ll [AArch64][SVE] Invert VSelect operand order and condition for predicated arithmetic operations 2022-02-17 16:01:17 +00:00
sve-fp-reduce.ll [AArch64] Regenerate more tests. NFC 2022-07-03 15:49:16 +01:00
sve-fp-rounding.ll
sve-fp-vselect.ll [AArch64][SVE] Fold vselect into predicated fmul, fsub and fadd 2022-02-03 13:43:15 +00:00
sve-fp.ll [SVE] Update patterns to commute FMLS multiplication operands 2022-03-01 12:53:14 -08:00
sve-fpext-load.ll [AArch64][SVE] Remove false register dependency for unary FP convert operations 2022-02-04 09:55:39 +00:00
sve-fptrunc-store.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-gather-scatter-addr-opts.ll [SVE] Move reg+reg gather/scatter addressing optimisations from lowering into DAG combine. 2022-04-29 17:42:33 +01:00
sve-gather-scatter-dag-combine.ll [AArch64][SVE] Break false dependencies for inactive lanes of unary operations 2021-07-26 15:01:21 +00:00
sve-gep.ll [SVE][CodeGen] Add patterns for ADD/SUB + element count 2021-10-13 11:36:15 +01:00
sve-implicit-zero-filling.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-insert-element.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
sve-insert-vector-to-predicate-load.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sve-insert-vector.ll [AArch64] NFC: Fix name mangling in sve-insert-vector.ll 2022-07-06 15:57:11 +00:00
sve-insr.ll
sve-int-arith-imm.ll [SVE] Use DUPM to handling more splat immediate cases. 2022-01-26 12:04:44 +00:00
sve-int-arith-pred.ll
sve-int-arith.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-int-div-pred.ll
sve-int-imm.ll
sve-int-log-imm.ll
sve-int-log-pred.ll
sve-int-log.ll [AArch64] Add support for various operations on nxv1i1 types. 2022-07-06 15:57:11 +00:00
sve-int-mad-pred.ll
sve-int-mul-pred.ll
sve-int-mulh-pred.ll
sve-int-pred-reduce.ll [AArch64][SVE] Zero other lanes when doing OR reduction on unpacked predicate using ptest. 2022-07-06 16:12:44 +00:00
sve-int-reduce-pred.ll
sve-int-reduce.ll [SelectionDAG] Enable WidenVecOp_VECREDUCE for scalable vector 2022-06-24 02:32:53 +00:00
sve-intrinsics-adr.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-bfloat.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-contiguous-prefetches.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-conversion.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-counting-bits.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-counting-elems-i32.ll [NFC][SVE] Add missing tests for i32 INC/DEC patterns. 2021-12-17 13:13:36 +00:00
sve-intrinsics-counting-elems.ll [AArch64] Remove references to Streaming SVE from target features. 2022-05-31 16:25:01 +02:00
sve-intrinsics-create-tuple.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-dup-x.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ff-gather-loads-32bit-scaled-offsets.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ff-gather-loads-32bit-unscaled-offsets.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ff-gather-loads-64bit-scaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ff-gather-loads-64bit-unscaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ff-gather-loads-vector-base-imm-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ff-gather-loads-vector-base-scalar-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ffr-manipulation.ll
sve-intrinsics-fp-arith-imm.ll [llvm][AArch64][SVE] Fold literals into math instructions 2021-10-17 10:57:04 +00:00
sve-intrinsics-fp-arith-merging.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-fp-arith.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-fp-compares.ll [AArch64][SVE] Add ISel patterns for floating point compare with zero instructions 2021-07-08 10:46:12 +00:00
sve-intrinsics-fp-converts.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-fp-reduce.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-loads-32bit-scaled-offsets.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-loads-64bit-scaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-loads-64bit-unscaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-loads-vector-base-imm-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-loads-vector-base-scalar-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-index.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-intrinsics-insert-extract-tuple.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-int-arith-imm.ll [SVE] Use DUPM to handling more splat immediate cases. 2022-01-26 12:04:44 +00:00
sve-intrinsics-int-arith-merging.ll [AArch64][SVE] Remove BIC from logical operation DestructiveBinaryComm patterns 2022-04-22 15:07:55 +01:00
sve-intrinsics-int-arith.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-intrinsics-int-compares-with-imm.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-int-compares.ll [AArc64] Legalisation of compares and truncates of nxv1i1 types. 2022-07-07 07:39:27 +00:00
sve-intrinsics-ld1-addressing-mode-reg-imm.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ld1-addressing-mode-reg-reg.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ld1.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ld1ro-addressing-mode-reg-reg.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ld1ro.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ldN-reg+imm-addr-mode.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ldN-reg+reg-addr-mode.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll [AArch64] Remove references to Streaming SVE from target features. 2022-05-31 16:25:01 +02:00
sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll [AArch64] Remove references to Streaming SVE from target features. 2022-05-31 16:25:01 +02:00
sve-intrinsics-ldst-ext.ll [AArch64][SelectionDAG] Refactor to support more scalable vector extending loads 2022-03-27 21:18:01 +08:00
sve-intrinsics-loads-ff.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-loads-nf.ll
sve-intrinsics-loads.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-logical-imm.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-logical.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-mask-ldst-ext.ll [AArch64][SelectionDAG] Refactor to support more scalable vector extending loads 2022-03-27 21:18:01 +08:00
sve-intrinsics-matmul-fp32.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-matmul-fp64.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-matmul-int8.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-perm-select-matmul-fp64.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-perm-select.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sve-intrinsics-pred-creation.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-pred-operations.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-pred-testing.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-reinterpret-no-streaming.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-intrinsics-reinterpret.ll [AArch64] Add support for various operations on nxv1i1 types. 2022-07-06 15:57:11 +00:00
sve-intrinsics-reversal.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-scalar-to-vec.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-scatter-stores-64bit-scaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-scatter-stores-64bit-unscaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-scatter-stores-vector-base-imm-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-scatter-stores-vector-base-scalar-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-sel.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-shifts-merging.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-shifts.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-sqdec.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-sqinc.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-st1-addressing-mode-reg-imm.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-st1-addressing-mode-reg-reg.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-st1.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-stN-reg-imm-addr-mode.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-stN-reg-reg-addr-mode.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-stores.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-unpred-form.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-uqdec.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-uqinc.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-intrinsics-while.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve-ld-post-inc.ll [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED. 2022-02-10 17:22:01 +00:00
sve-ld1-addressing-mode-reg-imm.ll
sve-ld1-addressing-mode-reg-reg.ll [AArch64][SVE] Add missing load/store patterns for unpacked bfloat vectors. 2021-09-22 09:45:33 +01:00
sve-ld1r.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-ld1r.mir [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory 2021-07-06 12:03:54 +00:00
sve-ldN.mir [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo 2022-02-17 17:09:17 +00:00
sve-ldnf1.mir [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
sve-ldstnt1.mir [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
sve-localstackalloc.mir
sve-lsr-scaled-index-addressing-mode.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-masked-gather-32b-signed-scaled.ll
sve-masked-gather-32b-signed-unscaled.ll
sve-masked-gather-32b-unsigned-scaled.ll
sve-masked-gather-32b-unsigned-unscaled.ll
sve-masked-gather-64b-scaled.ll
sve-masked-gather-64b-unscaled.ll
sve-masked-gather-legalize.ll [SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD. 2022-02-10 14:30:28 +00:00
sve-masked-gather-vec-plus-imm.ll
sve-masked-gather-vec-plus-reg.ll
sve-masked-gather.ll [SVE] Add support for non-element-type sized scaling when lowering MGATHER/MSCATTER. 2022-04-14 11:54:46 +01:00
sve-masked-ldst-nonext.ll [SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD. 2022-02-10 14:30:28 +00:00
sve-masked-ldst-sext.ll [AArch64] Regenerate 3 codegen test files. NFC 2022-06-16 18:23:05 +01:00
sve-masked-ldst-trunc.ll
sve-masked-ldst-zext.ll [AArch64][InstCombine] Fold MLOAD and zero extensions into MLOAD 2022-04-06 20:50:42 +08:00
sve-masked-scatter-32b-scaled.ll
sve-masked-scatter-32b-unscaled.ll
sve-masked-scatter-64b-scaled.ll
sve-masked-scatter-64b-unscaled.ll
sve-masked-scatter-legalize.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-masked-scatter-vec-plus-imm.ll
sve-masked-scatter-vec-plus-reg.ll
sve-masked-scatter.ll [SVE] Add support for non-element-type sized scaling when lowering MGATHER/MSCATTER. 2022-04-14 11:54:46 +01:00
sve-merging-stores.ll
sve-no-typesize-warnings.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sve-pfalse-machine-cse.mir [AArch64][SVE] Implement PFALSE with explicit AArch64ISD node. 2022-01-27 10:30:13 +00:00
sve-pred-arith.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll [SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD. 2022-02-10 14:30:28 +00:00
sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll [SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD. 2022-02-10 14:30:28 +00:00
sve-pred-log.ll [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors 2021-11-17 08:55:11 +00:00
sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
sve-pseudos-expand-undef.mir
sve-ptest-removal-brk.ll
sve-ptest-removal-cmpeq.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmpeq.mir
sve-ptest-removal-cmpge.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmpgt.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmphi.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmphs.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmple.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmplo.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmpls.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmplt.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-cmpne.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-ptest-removal-match.ll
sve-ptest-removal-pfirst-pnext.ll [AArch64][SVE] Remove redundant PTEST following PNEXT/PFIRST 2021-10-05 15:10:48 +00:00
sve-ptest-removal-rdffr.mir
sve-ptest-removal-whilege.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
sve-ptest-removal-whilegt.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
sve-ptest-removal-whilehi.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
sve-ptest-removal-whilehs.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
sve-ptest-removal-whilele.mir
sve-ptest-removal-whilelo.mir
sve-ptest-removal-whilels.mir
sve-ptest-removal-whilelt.mir
sve-ptest-removal-whilerw.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
sve-ptest-removal-whilewr.mir [AArch64] Fix subtarget features for tests. NFC 2022-07-12 11:03:40 +01:00
sve-punpklo-combine.ll [IR] Move vector.insert/vector.extract out of experimental namespace 2022-06-27 10:48:45 +00:00
sve-redundant-store.ll
sve-rev.ll
sve-sdiv-pow2.ll [AArch64][SVE] Generate ASRD instructions for power of 2 signed divides 2021-11-26 11:08:27 +00:00
sve-select.ll [AArch64] Make nxv1i1 types a legal type for SVE. 2022-07-01 15:11:13 +00:00
sve-setcc.ll [AArch64][SVE] Ensure PTEST operands have type nxv16i1 2022-07-12 09:27:59 +01:00
sve-sext-zext.ll [LegalizeDAG] Fix TypeSize conversion error when expanding SIGN_EXTEND_INREG 2022-04-30 19:21:48 +01:00
sve-smulo-sdnode.ll [SVE] By using SEL when orring predicates we forgo the need for a PTRUE. 2022-01-31 19:39:23 +00:00
sve-split-extract-elt.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
sve-split-fcvt.ll [AArch64][SVE] Remove false register dependency for unary FP convert operations 2022-02-04 09:55:39 +00:00
sve-split-fp-reduce.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-split-insert-elt.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
sve-split-int-pred-reduce.ll [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
sve-split-int-reduce.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-split-load.ll [SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD. 2022-02-10 14:30:28 +00:00
sve-split-store.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-split-trunc.ll
sve-srem-combine-loop.ll [DAGCombiner] When combining REM ensure optimized div nodes are unique 2021-12-01 11:24:26 +00:00
sve-st1-addressing-mode-reg-imm.ll [DAGCombiner] Fold `ty1 extract_vector(ty2 splat(V)) -> ty1 splat(V)` 2022-02-09 14:30:01 +00:00
sve-st1-addressing-mode-reg-reg.ll [AArch64][SVE] Add missing load/store patterns for unpacked bfloat vectors. 2021-09-22 09:45:33 +01:00
sve-stN.mir [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo 2022-02-17 17:09:17 +00:00
sve-stepvector.ll [SelectionDAG] Add support to widen ISD::STEP_VECTOR operations. 2022-05-24 22:42:37 +01:00
sve-tailcall.ll
sve-trunc.ll [AArc64] Legalisation of compares and truncates of nxv1i1 types. 2022-07-07 07:39:27 +00:00
sve-umulo-sdnode.ll [SVE] By using SEL when orring predicates we forgo the need for a PTRUE. 2022-01-31 19:39:23 +00:00
sve-unary-movprfx.ll [AArch64][SVE] Break false dependencies for inactive lanes of FP unary operations 2021-11-15 09:15:21 +00:00
sve-varargs-callee-broken.ll
sve-varargs-caller-broken.ll
sve-varargs.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
sve-vecreduce-fold.ll [AArch64][SVE] Zero other lanes when doing OR reduction on unpacked predicate using ptest. 2022-07-06 16:12:44 +00:00
sve-vector-splat.ll [SVE] Optimize new cases for lowerConvertToSVBool 2022-05-09 10:17:57 +00:00
sve-vl-arith.ll [SVE][CodeGen] Add patterns for ADD/SUB + element count 2021-10-13 11:36:15 +01:00
sve-vscale-attr.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
sve-vscale-combine.ll
sve-vscale.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
sve-vselect-fold.ll [AArch64][SVE] Folds VSELECT if the predicate is all active. 2022-01-27 15:58:56 +00:00
sve-vselect-imm.ll [SVE] Use CPY to zero active lanes of a floating point vector. 2022-07-01 00:59:00 +01:00
sve-widen-scalable-vectortype.ll
sve-zeroinit.ll [AArch64] Make nxv1i1 types a legal type for SVE. 2022-07-01 15:11:13 +00:00
sve2-bitwise-ternary.ll
sve2-fcopysign.ll [AArch64][NEON][SVE] Lower FCOPYSIGN using AArch64ISD::BSP 2022-02-07 14:35:26 +00:00
sve2-int-addsub-long.ll
sve2-int-mul.ll [SVE] Use DUPM to handling more splat immediate cases. 2022-01-26 12:04:44 +00:00
sve2-int-mulh.ll
sve2-intrinsics-binary-narrowing-add-sub.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-binary-narrowing-shr.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-bit-permutation.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-character-match.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-complex-dot.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-contiguous-conflict-detection.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-crypto.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-fp-converts.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-fp-int-binary-logarithm.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-fp-widening-mul-acc.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-int-arith-imm.ll [AArch64] Regenerate some test checks. NFC 2021-09-08 11:08:32 +01:00
sve2-intrinsics-int-mul-lane.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-non-widening-pairwise-arith.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-nt-gather-loads-32bit-unscaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-nt-gather-loads-64bit-unscaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-nt-gather-loads-vector-base-scalar-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-nt-scatter-stores-32bit-unscaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-nt-scatter-stores-64bit-scaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-nt-scatter-stores-64bit-unscaled-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-nt-scatter-stores-vector-base-scalar-offset.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-perm-tb.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-polynomial-arithmetic-128.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-polynomial-arithmetic.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-psel.ll [AArch64][SME] Add SVE2 psel, uclamp, sclamp and revd IR intrinsics 2022-06-28 10:25:06 +01:00
sve2-intrinsics-revd.ll [AArch64][SME] Add SVE2 psel, uclamp, sclamp and revd IR intrinsics 2022-06-28 10:25:06 +01:00
sve2-intrinsics-sclamp.ll [AArch64][SME] Add SVE2 psel, uclamp, sclamp and revd IR intrinsics 2022-06-28 10:25:06 +01:00
sve2-intrinsics-uclamp.ll [AArch64][SME] Add SVE2 psel, uclamp, sclamp and revd IR intrinsics 2022-06-28 10:25:06 +01:00
sve2-intrinsics-unary-narrowing.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-uniform-complex-arith.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-uniform-dsp-zeroing.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-uniform-dsp.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-vec-hist-count.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-while.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-widening-complex-int-arith.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-widening-dsp.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-intrinsics-widening-pairwise-arith.ll [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. 2022-06-27 00:07:00 +01:00
sve2-mla-indexed.ll
sve2-mla-unpredicated.ll
sve2-rsra.ll [AArch64][SVE] Match (add x (urshr/srshr y c)) -> ursra/srsra x y c 2022-06-29 12:10:50 +00:00
sve2-sra.ll [AArch64][SVE] Match (add x (lsr/asr y c)) -> usra/ssra x y c 2022-06-23 14:56:21 +00:00
sve2-unary-movprfx.ll [AArch64] Regenerate some test checks. NFC 2021-09-08 11:08:32 +01:00
swap-compare-operands.ll
swift-async-pei.ll AArch64: correct epilogue/prologue emission for swift async 2022-03-09 18:41:10 +00:00
swift-async-reg.ll
swift-async-unwind.ll
swift-async-win.ll AArch64: modify Swift async frame record storage on Windows 2022-04-30 09:01:33 -07:00
swift-async.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
swift-dynamic-async-frame.ll Teach the backend to make references to swift_async_extendedFramePointerFlags weak if it emits it 2021-12-15 10:02:06 -08:00
swift-error.ll
swift-return.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
swiftcc.ll
swifterror.ll [DAGCombine] Add node in the worklist in topological order in CombineTo 2022-05-07 16:24:31 +00:00
swiftself-scavenger.ll
swiftself.ll Tail calls: look through AssertZExt to find register copy. 2022-04-11 12:24:47 +01:00
swifttail-arm64_32.ll AArch64: use 4-byte slots for arm64_32 pointers in a tail call 2021-07-13 11:08:59 +01:00
swifttail-async.ll
swifttail-call.ll [AArch64] Async unwind - Adjust unwind info in AArch64LoadStoreOptimizer 2022-04-18 12:09:44 +01:00
switch-unreachable-default.ll
tagged-globals-pic.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
tagged-globals-static.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
tagp.ll
tail-call-unused-zext.ll
tail-call.ll [AArch64] Async unwind - Adjust unwind info in AArch64LoadStoreOptimizer 2022-04-18 12:09:44 +01:00
tail-dup-redundant-phi.mir [SSAUpdaterImpl] Do not generate phi node with all the same incoming values 2022-06-03 12:24:33 +07:00
tailcall-bitcast-memcpy.ll
tailcall-ccmismatch.ll
tailcall-explicit-sret.ll
tailcall-fastisel.ll
tailcall-implicit-sret.ll
tailcall-mem-intrinsics.ll
tailcall-ssp-split-debug.ll Reapply: StackProtector: ignore debug insts when splitting blocks. 2022-02-14 10:58:22 +00:00
tailcall-string-rvo.ll
tailcall_misched_graph.ll
tailcc-notail.ll
tailcc-tail-call.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
taildup-cfi.ll
taildup-inst-dup-loc.mir [IR] Enable opaque pointers by default 2022-06-02 09:40:56 +02:00
tailmerging_in_mbp.ll
tbi.ll
tbl-loops.ll [AArch64] Lower 3 and 4 sources buildvectors to TBL 2022-03-26 21:10:43 +00:00
tbz-tbnz.ll
tiny-model-pic.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
tiny-model-static.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
tiny_supported.ll
tme.ll
trunc-v1i64.ll
tst-br.ll [AArch64] Regenerate some test checks. NFC 2021-09-08 09:14:01 +01:00
typepromotion-overflow.ll [TypePromotion] Extend TypePromotion::isSafeWrap 2021-11-14 11:18:31 +00:00
typepromotion-phisret.ll [TypePromotion] Promote undef by converting to 0. 2022-05-12 09:09:24 -07:00
typepromotion-signed.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
uadd_sat.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
uadd_sat_plus.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
uadd_sat_vec.ll [AArch64] Add `foldOverflowCheck` DAG combine 2022-04-21 14:56:38 +01:00
uaddo.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
ubsantrap.ll [GlobalISel] Implement support for the "trap-func-name" attribute. 2021-09-20 14:32:01 -07:00
udivmodei5.ll [SelectionDAG] Emit calls to __divei4 and friends for division/remainder of large integers 2022-03-16 09:36:28 +00:00
umulo-128-legalisation-lowering.ll Extend `performANDCSELCombine` to `performANDORCSELCombine` 2022-03-04 15:09:59 +00:00
unfold-masked-merge-scalar-constmask-innerouter.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
unfold-masked-merge-scalar-constmask-interleavedbits.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
unfold-masked-merge-scalar-constmask-lowhigh.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
unfold-masked-merge-scalar-variablemask.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
unfold-masked-merge-vector-variablemask-const.ll [ISEL] Canonicalise constant splats to RHS. 2022-01-24 09:38:36 +00:00
unfold-masked-merge-vector-variablemask.ll Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants" 2022-01-18 08:40:20 +00:00
unreachable-emergency-spill-slot.mir
unwind-preserved-from-mir.mir [AArch64] Async unwind - function prologues 2022-03-24 16:16:44 +00:00
unwind-preserved.ll [AArch64] Async unwind - function epilogues 2022-04-12 16:50:50 +01:00
urem-lkk.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
urem-seteq-illegal-types.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
urem-seteq-nonzero.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
urem-seteq-optsize.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
urem-seteq-vec-nonsplat.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
urem-seteq-vec-nonzero.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
urem-seteq-vec-splat.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
urem-seteq-vec-tautological.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
urem-seteq.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
urem-vector-lkk.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
use-cr-result-of-dom-icmp-st.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
ushl_sat.ll [DAG] Fold (srl (shl x, c1), c2) -> and(shl/srl(x, c3), m) 2022-06-20 08:37:38 +01:00
usub_sat.ll
usub_sat_plus.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
usub_sat_vec.ll [AArch64] Fix sub with carry 2022-05-06 11:04:17 -07:00
v3f-to-int.ll
v8.4-atomic-128.ll AArch64: use ldp/stp for 128-bit atomic load/store in v.84 onwards 2021-09-20 09:50:11 +01:00
v8.5a-neon-frint3264-intrinsic.ll
v8.5a-scalar-frint3264-intrinsic.ll
vararg-tallcall.ll
variant-pcs.ll
vcvt-oversize.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
vec-extract-branch.ll
vec-libcalls.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
vec_cttz.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
vec_uaddo.ll [AArch64] Add `foldOverflowCheck` DAG combine 2022-04-21 14:56:38 +01:00
vec_umulo.ll Extend `performANDCSELCombine` to `performANDORCSELCombine` 2022-03-04 15:09:59 +00:00
vecreduce-add-legalization.ll [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`. 2022-05-12 22:17:23 +01:00
vecreduce-add.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
vecreduce-and-legalization.ll [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal 2022-07-07 09:33:54 +00:00
vecreduce-bool.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
vecreduce-fadd-legalization-strict.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
vecreduce-fadd-legalization.ll [AArch64] Use simd mov to materialize big fp constants 2022-03-04 11:34:20 -05:00
vecreduce-fadd.ll [AArch64] Use first op of FADDPv* instead of implicit def. 2022-03-03 13:32:09 +00:00
vecreduce-fmax-legalization-nan.ll
vecreduce-fmax-legalization.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
vecreduce-fmin-legalization.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
vecreduce-fmul-legalization-strict.ll
vecreduce-propagate-sd-flags.ll [DAG] visitINSERT_VECTOR_ELT - attempt to reconstruct BUILD_VECTOR before other fold interfere 2022-06-13 11:48:18 +01:00
vecreduce-umax-legalization.ll [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal 2022-07-07 09:33:54 +00:00
vector-fcopysign.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
vector-gep.ll [AArch64] Regenerate more tests. NFC 2022-07-03 15:49:16 +01:00
vector-global-i1.ll [AsmPrinter] Fix bit pattern for i1 vectors. 2022-07-06 12:56:47 -07:00
vector-insert-shuffle-cycle.ll
vector-op-scalarize-strict.ll [AArch64] Fix legalization of v1f64 strict_fsetcc and strict_fsetccs 2022-02-04 12:55:38 +00:00
vector-popcnt-128-ult-ugt.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
vector_merge_dep_check.ll [Tests] Fix incorrect noalias metadata 2021-09-18 20:51:00 +02:00
vector_splat-const-shift-of-constmasked.ll
vldn_shuffle.ll [InterleaveAccessPass] Handle multi-use binop shuffles 2022-07-10 17:24:37 +01:00
volatile-combine.ll AArch64: copy all parts of the mem operand across when combining a store 2021-08-19 18:26:39 +01:00
vselect-constants.ll [SchedModels][CortexA55] Add ASIMD integer instructions 2022-02-17 13:41:57 +03:00
vselect-ext.ll [AArch64] Try to re-use extended operand for SETCC with vector ops. 2022-07-07 16:50:00 -07:00
win-alloca-no-stack-probe.ll
win-alloca.ll
win-catchpad-nested-cxx.ll
win-tls.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
win64-jumptable.ll [AArch64] [COFF] Move jump tables back to the readonly section 2021-11-23 10:13:48 +02:00
win64-no-uwtable.ll
win64-nocfi.ll
win64_vararg.ll [AArch64] Regenerate more tests. NFC 2022-07-03 15:49:16 +01:00
win64_vararg_float.ll [AArch64] Regenerate more tests. NFC 2022-07-03 15:49:16 +01:00
win64_vararg_float_cc.ll [AArch64] Regenerate more tests. NFC 2022-07-03 15:49:16 +01:00
win64cc-backup-x18.ll
win_cst_pool.ll [MC] Make MCAsmInfo::isAcceptableChar reflect MCAsmInfo::doesAllowAtInName 2022-03-29 14:01:32 -07:00
windows-SEH-support.ll
windows-extern-weak.ll
windows-trap.ll
wineh-frame-predecrement.mir
wineh-frame-scavenge.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame0.mir
wineh-frame1.mir
wineh-frame2.mir
wineh-frame3.mir
wineh-frame4.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame5.mir
wineh-frame6.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame7.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame8.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-mingw.ll
wineh-save-lrpair1.mir
wineh-save-lrpair2.mir
wineh-save-lrpair3.mir
wineh-try-catch-cbz.ll
wineh-try-catch-nobase.ll [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted 2021-08-03 02:28:46 -07:00
wineh-try-catch-realign.ll
wineh-try-catch-vla.ll
wineh-try-catch.ll
wineh-unwindhelp-via-fp.ll
wineh1.mir [MC] [Win64EH] Try writing an ARM64 "packed epilog" even if the epilog doesn't share opcodes with the prolog 2022-05-17 00:41:39 +03:00
wineh2.mir [MC] [Win64EH] Try writing an ARM64 "packed epilog" even if the epilog doesn't share opcodes with the prolog 2022-05-17 00:41:39 +03:00
wineh3.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh4.mir [MC] [Win64EH] Check for matches between epilogs and the prolog on ARM64 2022-05-17 00:41:39 +03:00
wineh5.mir [MC] [Win64EH] Try writing an ARM64 "packed epilog" even if the epilog doesn't share opcodes with the prolog 2022-05-17 00:41:39 +03:00
wineh6.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh7.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh8.mir [MC] [Win64EH] Check for matches between epilogs and the prolog on ARM64 2022-05-17 00:41:39 +03:00
wineh_shrinkwrap.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wrong-callee-save-size-after-livedebugvariables.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wrong_debug_loc_after_regalloc.ll
xbfiz.ll
xor.ll [AArch64] Make -mcpu=generic schedule for an in-order core 2021-10-09 15:58:31 +01:00
xray-attribute-instrumentation.ll [XRay][test] Clean up llc RUN lines 2022-01-21 17:00:03 -08:00
xray-omit-function-index.ll [XRay][test] Clean up llc RUN lines 2022-01-21 17:00:03 -08:00
xray-partial-instrumentation-skip-entry.ll [XRay][test] Clean up llc RUN lines 2022-01-21 17:00:03 -08:00
xray-partial-instrumentation-skip-exit.ll [XRay][test] Clean up llc RUN lines 2022-01-21 17:00:03 -08:00
xray-tail-call-sled.ll [XRay][test] Clean up llc RUN lines 2022-01-21 17:00:03 -08:00
zero-call-used-regs.ll [AArch64] Use proper instruction mnemonics for FPRs 2022-05-20 12:02:26 -07:00
zero-reg.ll
zext-logic-shift-load.ll
zext-reg-coalesce.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
zext-to-tbl.ll [AArch64] Add test cases where zext can be lowered to series of tbl. 2022-02-25 15:36:32 +00:00

README

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.