295 lines
8.9 KiB
TableGen
295 lines
8.9 KiB
TableGen
//===--- PPCSchedPredicates.td - PowerPC Scheduling Preds -*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Automatically generated file, do not edit!
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//
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// This file defines scheduling predicate definitions that are used by the
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// PowerPC subtargets.
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//===----------------------------------------------------------------------===//
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// Identify instructions that write BF pipelines with 7 cycles.
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def P10W_BF_7C_Pred : MCSchedPredicate<
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CheckOpcode<[FADD,
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FADDS,
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FADDS_rec,
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FADD_rec,
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FCFID,
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FCFIDS,
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FCFIDS_rec,
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FCFIDU,
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FCFIDUS,
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FCFIDUS_rec,
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FCFIDU_rec,
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FCFID_rec,
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FCTID,
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FCTIDU,
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FCTIDUZ,
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FCTIDUZ_rec,
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FCTIDU_rec,
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FCTIDZ,
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FCTIDZ_rec,
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FCTID_rec,
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FCTIW,
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FCTIWU,
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FCTIWUZ,
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FCTIWUZ_rec,
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FCTIWU_rec,
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FCTIWZ,
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FCTIWZ_rec,
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FCTIW_rec,
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FMADD,
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FMADDS,
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FMADDS_rec,
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FMADD_rec,
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FMSUB,
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FMSUBS,
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FMSUBS_rec,
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FMSUB_rec,
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FMUL,
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FMULS,
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FMULS_rec,
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FMUL_rec,
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FNMADD,
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FNMADDS,
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FNMADDS_rec,
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FNMADD_rec,
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FNMSUB,
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FNMSUBS,
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FNMSUBS_rec,
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FNMSUB_rec,
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FRE,
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FRES,
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FRES_rec,
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FRE_rec,
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FRIMD, FRIMS,
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FRIMD_rec, FRIMS_rec,
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FRIND, FRINS,
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FRIND_rec, FRINS_rec,
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FRIPD, FRIPS,
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FRIPD_rec, FRIPS_rec,
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FRIZD, FRIZS,
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FRIZD_rec, FRIZS_rec,
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FRSP,
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FRSP_rec,
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FRSQRTE,
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FRSQRTES,
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FRSQRTES_rec,
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FRSQRTE_rec,
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FSELD, FSELS,
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FSELD_rec, FSELS_rec,
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FSUB,
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FSUBS,
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FSUBS_rec,
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FSUB_rec,
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VADDFP,
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VCFSX, VCFSX_0,
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VCFUX, VCFUX_0,
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VCTSXS, VCTSXS_0,
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VCTUXS, VCTUXS_0,
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VEXPTEFP,
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VEXPTEFP,
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VLOGEFP,
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VMADDFP,
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VNMSUBFP,
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VREFP,
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VRFIM,
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VRFIN,
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VRFIP,
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VRFIZ,
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VRSQRTEFP,
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VSUBFP,
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XSADDDP,
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XSADDSP,
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XSCVDPHP,
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XSCVDPSP,
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XSCVDPSPN,
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XSCVDPSXDS, XSCVDPSXDSs,
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XSCVDPSXWS, XSCVDPSXWSs,
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XSCVDPUXDS, XSCVDPUXDSs,
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XSCVDPUXWS, XSCVDPUXWSs,
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XSCVSPDP,
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XSCVSXDDP,
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XSCVSXDSP,
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XSCVUXDDP,
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XSCVUXDSP,
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XSMADDADP,
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XSMADDASP,
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XSMADDMDP,
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XSMADDMSP,
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XSMSUBADP,
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XSMSUBASP,
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XSMSUBMDP,
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XSMSUBMSP,
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XSMULDP,
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XSMULSP,
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XSNMADDADP,
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XSNMADDASP,
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XSNMADDMDP,
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XSNMADDMSP,
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XSNMSUBADP,
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XSNMSUBASP,
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XSNMSUBMDP,
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XSNMSUBMSP,
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XSRDPI,
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XSRDPIC,
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XSRDPIM,
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XSRDPIP,
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XSRDPIZ,
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XSREDP,
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XSRESP,
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XSRSP,
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XSRSQRTEDP,
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XSRSQRTESP,
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XSSUBDP,
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XSSUBSP,
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XVADDDP,
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XVADDSP,
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XVCVDPSP,
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XVCVDPSXDS,
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XVCVDPSXWS,
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XVCVDPUXDS,
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XVCVDPUXWS,
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XVCVSPBF16,
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XVCVSPDP,
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XVCVSPHP,
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XVCVSPSXDS,
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XVCVSPSXWS,
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XVCVSPUXDS,
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XVCVSPUXWS,
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XVCVSXDDP,
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XVCVSXDSP,
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XVCVSXWDP,
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XVCVSXWSP,
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XVCVUXDDP,
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XVCVUXDSP,
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XVCVUXWDP,
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XVCVUXWSP,
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XVMADDADP,
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XVMADDASP,
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XVMADDMDP,
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XVMADDMSP,
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XVMSUBADP,
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XVMSUBASP,
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XVMSUBMDP,
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XVMSUBMSP,
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XVMULDP,
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XVMULSP,
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XVNMADDADP,
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XVNMADDASP,
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XVNMADDMDP,
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XVNMADDMSP,
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XVNMSUBADP,
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XVNMSUBASP,
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XVNMSUBMDP,
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XVNMSUBMSP,
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XVRDPI,
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XVRDPIC,
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XVRDPIM,
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XVRDPIP,
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XVRDPIZ,
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XVREDP,
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XVRESP,
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XVRSPI,
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XVRSPIC,
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XVRSPIM,
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XVRSPIP,
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XVRSPIZ,
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XVRSQRTEDP,
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XVRSQRTESP,
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XVSUBDP,
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XVSUBSP]>
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>;
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// Identify instructions that write CY pipelines with 7 cycles.
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def P10W_CY_7C_Pred : MCSchedPredicate<
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CheckOpcode<[CFUGED,
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CNTLZDM,
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CNTTZDM,
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PDEPD,
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PEXTD,
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VCFUGED,
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VCIPHER,
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VCIPHERLAST,
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VCLZDM,
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VCTZDM,
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VGNB,
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VNCIPHER,
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VNCIPHERLAST,
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VPDEPD,
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VPEXTD,
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VPMSUMB,
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VPMSUMD,
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VPMSUMH,
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VPMSUMW,
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VSBOX]>
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>;
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// Identify instructions that write MM pipelines with 10 cycles.
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def P10W_MM_10C_Pred : MCSchedPredicate<
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CheckOpcode<[PMXVBF16GER2,
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PMXVBF16GER2NN,
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PMXVBF16GER2NP,
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PMXVBF16GER2PN,
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PMXVBF16GER2PP,
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PMXVF16GER2,
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PMXVF16GER2NN,
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PMXVF16GER2NP,
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PMXVF16GER2PN,
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PMXVF16GER2PP,
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PMXVF32GER,
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PMXVF32GERNN,
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PMXVF32GERNP,
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PMXVF32GERPN,
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PMXVF32GERPP,
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PMXVF64GER,
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PMXVF64GERNN,
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PMXVF64GERNP,
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PMXVF64GERPN,
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PMXVF64GERPP,
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PMXVI16GER2,
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PMXVI16GER2PP,
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PMXVI16GER2S,
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PMXVI16GER2SPP,
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PMXVI4GER8,
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PMXVI4GER8PP,
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PMXVI8GER4,
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PMXVI8GER4PP,
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PMXVI8GER4SPP,
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XVBF16GER2,
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XVBF16GER2NN,
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XVBF16GER2NP,
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XVBF16GER2PN,
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XVBF16GER2PP,
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XVF16GER2,
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XVF16GER2NN,
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XVF16GER2NP,
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XVF16GER2PN,
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XVF16GER2PP,
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XVF32GER,
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XVF32GERNN,
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XVF32GERNP,
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XVF32GERPN,
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XVF32GERPP,
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XVF64GER,
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XVF64GERNN,
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XVF64GERNP,
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XVF64GERPN,
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XVF64GERPP,
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XVI16GER2,
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XVI16GER2PP,
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XVI16GER2S,
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XVI16GER2SPP,
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XVI4GER8,
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XVI4GER8PP,
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XVI8GER4,
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XVI8GER4PP,
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XVI8GER4SPP,
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XXMFACC,
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XXMFACC,
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XXMTACC,
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XXSETACCZ]>
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>;
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