120 lines
4.4 KiB
C++
120 lines
4.4 KiB
C++
//=- RISCVMachineFunctionInfo.h - RISCV machine function info -----*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares RISCV-specific per-machine-function information.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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namespace llvm {
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class RISCVMachineFunctionInfo;
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namespace yaml {
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struct RISCVMachineFunctionInfo final : public yaml::MachineFunctionInfo {
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int VarArgsFrameIndex;
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int VarArgsSaveSize;
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bool IsEntryFunction = false;
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RISCVMachineFunctionInfo() = default;
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RISCVMachineFunctionInfo(const llvm::RISCVMachineFunctionInfo &MFI);
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void mappingImpl(yaml::IO &YamlIO) override;
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~RISCVMachineFunctionInfo() = default;
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};
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template <> struct MappingTraits<RISCVMachineFunctionInfo> {
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static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI) {
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YamlIO.mapOptional("varArgsFrameIndex", MFI.VarArgsFrameIndex);
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YamlIO.mapOptional("varArgsSaveSize", MFI.VarArgsSaveSize);
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YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
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}
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};
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} // end namespace yaml
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/// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo
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/// and contains private RISCV-specific information for each MachineFunction.
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class RISCVMachineFunctionInfo : public MachineFunctionInfo {
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private:
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/// FrameIndex for start of varargs area
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int VarArgsFrameIndex = 0;
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/// Size of the save area used for varargs
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int VarArgsSaveSize = 0;
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/// OpenCL kernel. i.e. functions called by the hardware and not called
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/// by other functions.
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bool IsEntryFunction = false;
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/// FrameIndex used for transferring values between 64-bit FPRs and a pair
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/// of 32-bit GPRs via the stack.
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int MoveF64FrameIndex = -1;
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/// FrameIndex of the spill slot for the scratch register in BranchRelaxation.
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int BranchRelaxationScratchFrameIndex = -1;
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/// Size of any opaque stack adjustment due to save/restore libcalls.
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unsigned LibCallStackSize = 0;
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/// Registers that have been sign extended from i32.
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SmallVector<Register, 8> SExt32Registers;
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public:
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RISCVMachineFunctionInfo(const MachineFunction &MF) : IsEntryFunction(
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MF.getFunction().getCallingConv() == CallingConv::VENTUS_KERNEL) {}
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MachineFunctionInfo *
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clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
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const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
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const override;
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int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
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void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
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unsigned getVarArgsSaveSize() const { return VarArgsSaveSize; }
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void setVarArgsSaveSize(int Size) { VarArgsSaveSize = Size; }
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bool isEntryFunction() const { return IsEntryFunction; }
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int getMoveF64FrameIndex(MachineFunction &MF) {
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if (MoveF64FrameIndex == -1)
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MoveF64FrameIndex =
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MF.getFrameInfo().CreateStackObject(8, Align(8), false);
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return MoveF64FrameIndex;
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}
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int getBranchRelaxationScratchFrameIndex() const {
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return BranchRelaxationScratchFrameIndex;
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}
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void setBranchRelaxationScratchFrameIndex(int Index) {
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BranchRelaxationScratchFrameIndex = Index;
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}
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unsigned getLibCallStackSize() const { return LibCallStackSize; }
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void setLibCallStackSize(unsigned Size) { LibCallStackSize = Size; }
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bool useSaveRestoreLibCalls(const MachineFunction &MF) const {
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// We cannot use fixed locations for the callee saved spill slots if the
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// function uses a varargs save area, or is an interrupt handler.
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return MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
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VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall() &&
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!MF.getFunction().hasFnAttribute("interrupt");
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}
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void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI);
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void addSExt32Register(Register Reg);
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bool isSExt32Register(Register Reg) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
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