391 lines
14 KiB
C++
391 lines
14 KiB
C++
//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about RISCV target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetMachine.h"
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "RISCV.h"
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#include "RISCVMachineFunctionInfo.h"
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#include "RISCVMacroFusion.h"
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#include "RISCVTargetObjectFile.h"
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#include "RISCVTargetTransformInfo.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/MIRParser/MIParser.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/PassManager.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Passes/PassBuilder.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/IPO.h"
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#include <optional>
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using namespace llvm;
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static cl::opt<bool> EnableRedundantCopyElimination(
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"riscv-enable-copyelim",
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cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
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cl::Hidden);
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// FIXME: Unify control over GlobalMerge.
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static cl::opt<cl::boolOrDefault>
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EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
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cl::desc("Enable the global merge pass"));
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static cl::opt<bool>
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EnableMachineCombiner("riscv-enable-machine-combiner",
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cl::desc("Enable the machine combiner pass"),
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cl::init(true), cl::Hidden);
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
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RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
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auto *PR = PassRegistry::getPassRegistry();
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initializeGlobalISel(*PR);
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initializeRISCVMakeCompressibleOptPass(*PR);
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initializeRISCVCodeGenPreparePass(*PR);
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initializeRISCVMergeBaseOffsetOptPass(*PR);
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initializeRISCVSExtWRemovalPass(*PR);
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initializeRISCVPreRAExpandPseudoPass(*PR);
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initializeRISCVExpandPseudoPass(*PR);
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initializeVentusPrintfRuntimeBindingPass(*PR);
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}
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static StringRef computeDataLayout(const Triple &TT, StringRef CPU) {
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// if (CPU == "ventus-gpgpu")
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// return "e-m:e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256"
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// "-v256:256-v512:512-v1024:1024-n32:64-S128-A5-G1";
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bool IsRV32 = TT.isRISCV32();
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if(!IsRV32)
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return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128-A5-G1";
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assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
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return "e-m:e-p:32:32-i64:64-n32-S128-A5-G1";
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}
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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std::optional<Reloc::Model> RM) {
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return RM.value_or(Reloc::Static);
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}
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RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T, computeDataLayout(TT, CPU), TT, CPU, FS, Options,
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getEffectiveRelocModel(TT, RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
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initAsmInfo();
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// RISC-V supports the MachineOutliner.
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setMachineOutliner(true);
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setSupportsDefaultOutlining(true);
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}
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const RISCVSubtarget *
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RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute TuneAttr = F.getFnAttribute("tune-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU =
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CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
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std::string TuneCPU =
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TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
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std::string FS =
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FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
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std::string Key = CPU + TuneCPU + FS;
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auto &I = SubtargetMap[Key];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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auto ABIName = Options.MCOptions.getABIName();
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if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
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F.getParent()->getModuleFlag("target-abi"))) {
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auto TargetABI = RISCVABI::getTargetABI(ABIName);
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if (TargetABI != RISCVABI::ABI_Unknown &&
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ModuleTargetABI->getString() != ABIName) {
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report_fatal_error("-target-abi option != target-abi module flag");
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}
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ABIName = ModuleTargetABI->getString();
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}
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I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS,
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ABIName, *this);
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}
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return I.get();
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}
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void RISCVTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
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PB.registerPipelineParsingCallback(
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[this](StringRef PassName, ModulePassManager &PM,
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ArrayRef<PassBuilder::PipelineElement>) {
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if (PassName == "ventus-printf-runtime-binding") {
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PM.addPass(VentusPrintfRuntimeBindingPass());
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return true;
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}
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return false;
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});
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PB.registerPipelineEarlySimplificationEPCallback(
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[this](ModulePassManager &PM, OptimizationLevel Level) {
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PM.addPass(VentusPrintfRuntimeBindingPass());
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});
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}
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TargetTransformInfo
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RISCVTargetMachine::getTargetTransformInfo(const Function &F) const {
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return TargetTransformInfo(RISCVTTIImpl(this, F));
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}
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// A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
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// for all memory accesses, so it is reasonable to assume that an
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// implementation has no-op address space casts. If an implementation makes a
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// change to this, they can override it here.
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bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
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unsigned DstAS) const {
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return true;
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}
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namespace {
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class RISCVPassConfig : public TargetPassConfig {
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public:
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RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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RISCVTargetMachine &getRISCVTargetMachine() const {
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return getTM<RISCVTargetMachine>();
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}
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
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if (ST.hasMacroFusion()) {
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ScheduleDAGMILive *DAG = createGenericSchedLive(C);
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DAG->addMutation(createRISCVMacroFusionDAGMutation());
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return DAG;
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}
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return nullptr;
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}
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ScheduleDAGInstrs *
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createPostMachineScheduler(MachineSchedContext *C) const override {
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const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
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if (ST.hasMacroFusion()) {
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ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
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DAG->addMutation(createRISCVMacroFusionDAGMutation());
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return DAG;
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}
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return nullptr;
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addIRTranslator() override;
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bool addLegalizeMachineIR() override;
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bool addRegBankSelect() override;
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bool addGlobalInstructionSelect() override;
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void addPreEmitPass() override;
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void addPreEmitPass2() override;
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void addPreSched2() override;
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void addMachineSSAOptimization() override;
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void addPreRegAlloc() override;
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void addPostRegAlloc() override;
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};
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} // namespace
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TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new RISCVPassConfig(*this, PM);
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}
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void RISCVPassConfig::addIRPasses() {
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addPass(createVentusPrintfRuntimeBinding());
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createSROAPass());
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addPass(createInferAddressSpacesPass());
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}
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addPass(createAtomicExpandPass());
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createRISCVCodeGenPreparePass());
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TargetPassConfig::addIRPasses();
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}
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bool RISCVPassConfig::addPreISel() {
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if (TM->getOptLevel() != CodeGenOpt::None) {
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// Add a barrier before instruction selection so that we will not get
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// deleted block address after enabling default outlining. See D99707 for
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// more details.
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addPass(createBarrierNoopPass());
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}
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if (EnableGlobalMerge == cl::BOU_TRUE) {
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addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
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/* OnlyOptimizeForSize */ false,
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/* MergeExternalByDefault */ true));
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}
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return false;
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}
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bool RISCVPassConfig::addInstSelector() {
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addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
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return false;
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}
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bool RISCVPassConfig::addIRTranslator() {
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addPass(new IRTranslator(getOptLevel()));
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return false;
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}
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bool RISCVPassConfig::addLegalizeMachineIR() {
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addPass(new Legalizer());
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return false;
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}
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bool RISCVPassConfig::addRegBankSelect() {
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addPass(new RegBankSelect());
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return false;
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}
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bool RISCVPassConfig::addGlobalInstructionSelect() {
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addPass(new InstructionSelect(getOptLevel()));
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return false;
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}
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void RISCVPassConfig::addPreSched2() {}
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void RISCVPassConfig::addPreEmitPass() {
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addPass(createVentusInsertJoinToVBranchPass());
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// NOTE: This pass must be at the end of all optimization passes, as it
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// breaks the def-use chain!
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// Insert regext instruction for instruction whose register id is greater
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// than 31.
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addPass(createVentusRegextInsertionPass());
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addPass(&BranchRelaxationPassID);
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addPass(createRISCVMakeCompressibleOptPass());
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}
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void RISCVPassConfig::addPreEmitPass2() {
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addPass(createRISCVExpandPseudoPass());
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// Schedule the expansion of AMOs at the last possible moment, avoiding the
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// possibility for other passes to break the requirements for forward
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// progress in the LR/SC block.
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addPass(createRISCVExpandAtomicPseudoPass());
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}
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void RISCVPassConfig::addMachineSSAOptimization() {
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TargetPassConfig::addMachineSSAOptimization();
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if (EnableMachineCombiner)
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addPass(&MachineCombinerID);
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if (TM->getTargetTriple().getArch() == Triple::riscv64)
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addPass(createRISCVSExtWRemovalPass());
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}
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void RISCVPassConfig::addPreRegAlloc() {
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addPass(createRISCVPreRAExpandPseudoPass());
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createRISCVMergeBaseOffsetOptPass());
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addPass(createVentusVVInstrConversionPass());
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addPass(createVentusLegalizeLoadPass());
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}
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void RISCVPassConfig::addPostRegAlloc() {
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if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
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addPass(createRISCVRedundantCopyEliminationPass());
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// Copy form SPIRV
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// Do not work with OpPhi.
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disablePass(&BranchFolderPassID);
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disablePass(&MachineBlockPlacementID);
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TargetPassConfig::addPostRegAlloc();
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}
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yaml::MachineFunctionInfo *
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RISCVTargetMachine::createDefaultFuncInfoYAML() const {
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return new yaml::RISCVMachineFunctionInfo();
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}
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yaml::MachineFunctionInfo *
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RISCVTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
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const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
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return new yaml::RISCVMachineFunctionInfo(*MFI);
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}
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bool RISCVTargetMachine::parseMachineFunctionInfo(
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const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error, SMRange &SourceRange) const {
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const auto &YamlMFI =
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static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
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PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
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return false;
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}
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unsigned RISCVTargetMachine::getAssumedAddrSpace(const Value *V) const {
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const auto *LD = dyn_cast<LoadInst>(V);
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if (!LD)
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return RISCVAS::UNKNOWN_ADDRESS_SPACE;
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// It must be a generic pointer loaded.
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assert(V->getType()->isPointerTy() &&
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V->getType()->getPointerAddressSpace() == RISCVAS::FLAT_ADDRESS);
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const auto *Ptr = LD->getPointerOperand();
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if (Ptr->getType()->getPointerAddressSpace() != RISCVAS::CONSTANT_ADDRESS)
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return RISCVAS::UNKNOWN_ADDRESS_SPACE;
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// For a generic pointer loaded from the constant memory, it could be assumed
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// as a global pointer since the constant memory is only populated on the
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// host side. As implied by the offload programming model, only global
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// pointers could be referenced on the host side.
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return RISCVAS::GLOBAL_ADDRESS;
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}
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std::pair<const Value *, unsigned>
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RISCVTargetMachine::getPredicatedAddrSpace(const Value *V) const {
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assert(0 && "TODO!");
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}
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unsigned
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RISCVTargetMachine::getAddressSpaceForPseudoSourceKind(unsigned Kind) const {
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switch (Kind) {
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case PseudoSourceValue::Stack:
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case PseudoSourceValue::FixedStack:
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return RISCVAS::PRIVATE_ADDRESS;
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case PseudoSourceValue::ConstantPool:
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case PseudoSourceValue::GOT:
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case PseudoSourceValue::JumpTable:
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case PseudoSourceValue::GlobalValueCallEntry:
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case PseudoSourceValue::ExternalSymbolCallEntry:
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return RISCVAS::CONSTANT_ADDRESS;
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}
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return RISCVAS::FLAT_ADDRESS;
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}
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