104 lines
3.6 KiB
C++
104 lines
3.6 KiB
C++
//===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// RISC-V back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
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#define LLVM_LIB_TARGET_RISCV_RISCV_H
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class RISCVRegisterBankInfo;
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class RISCVSubtarget;
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class RISCVTargetMachine;
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class AsmPrinter;
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class FunctionPass;
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class InstructionSelector;
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class MCInst;
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class MCOperand;
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class MachineInstr;
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class MachineOperand;
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class PassRegistry;
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FunctionPass *createRISCVCodeGenPreparePass();
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void initializeRISCVCodeGenPreparePass(PassRegistry &);
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bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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AsmPrinter &AP);
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bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp, const AsmPrinter &AP);
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FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createRISCVMakeCompressibleOptPass();
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void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
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FunctionPass *createRISCVGatherScatterLoweringPass();
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void initializeRISCVGatherScatterLoweringPass(PassRegistry &);
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FunctionPass *createRISCVSExtWRemovalPass();
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void initializeRISCVSExtWRemovalPass(PassRegistry &);
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FunctionPass *createRISCVMergeBaseOffsetOptPass();
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void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
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FunctionPass *createRISCVExpandPseudoPass();
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void initializeRISCVExpandPseudoPass(PassRegistry &);
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FunctionPass *createRISCVPreRAExpandPseudoPass();
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void initializeRISCVPreRAExpandPseudoPass(PassRegistry &);
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FunctionPass *createRISCVExpandAtomicPseudoPass();
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void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
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FunctionPass *createRISCVRedundantCopyEliminationPass();
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void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
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FunctionPass *createVentusRegextInsertionPass();
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void initializeVentusRegextInsertionPass(PassRegistry &);
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FunctionPass *createVentusVVInstrConversionPass();
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void initializeVentusVVInstrConversionPass(PassRegistry &);
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InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
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RISCVSubtarget &,
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RISCVRegisterBankInfo &);
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}
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/// OpenCL uses address spaces to differentiate between
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/// various memory regions on the hardware. On the CPU
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/// all of the address spaces point to the same memory,
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/// however on the GPU, each address space points to
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/// a separate piece of memory that is unique from other
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/// memory locations.
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namespace RISCVAS {
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enum : unsigned {
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// The maximum value for flat, generic, local, private, constant and region.
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MAX_VENTUS_ADDRESS = 5,
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FLAT_ADDRESS = 0, ///< Address space for flat memory.
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GLOBAL_ADDRESS = 1, ///< Address space for global memory
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CONSTANT_ADDRESS = 1, ///< Address space for constant memory
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LOCAL_ADDRESS = 3, ///< Address space for local memory.
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PRIVATE_ADDRESS = 5, ///< Address space for private memory.
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// Some places use this if the address space can't be determined.
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UNKNOWN_ADDRESS_SPACE = ~0u,
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};
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}
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#endif
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