..
AsmParser
[llvm] Don't use Optional::getValue (NFC)
2022-06-20 22:45:45 -07:00
Disassembler
Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
2022-05-15 08:44:58 +08:00
MCTargetDesc
[NFC][Alignment] Use Align in MCAlignFragment
2022-06-15 12:31:00 +00:00
TargetInfo
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CMakeLists.txt
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCV.h
[RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly
2022-05-30 17:22:50 -07:00
RISCV.td
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVAsmPrinter.cpp
[RISCV] Lower case the first letter of LowerRISCVMachineOperandToMCOperand. NFC
2022-05-01 14:13:55 -07:00
RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.
2022-06-15 16:23:39 +08:00
RISCVFrameLowering.cpp
[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
2022-06-12 10:47:21 -07:00
RISCVFrameLowering.h
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
RISCVGatherScatterLowering.cpp
[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
2022-06-10 13:00:20 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Refactor code to remove some small wrapper methods and merge two functions together. NFC
2022-06-22 23:04:58 -07:00
RISCVISelDAGToDAG.h
[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
2022-06-03 09:00:17 -07:00
RISCVISelLowering.cpp
[RISCV] Add RISCVISD opcodes for the rest of get*Addr.
2022-06-22 09:21:07 -07:00
RISCVISelLowering.h
[RISCV] Add RISCVISD opcodes for the rest of get*Addr.
2022-06-22 09:21:07 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Delete unexercised VL=0 vsetvli compatibility logic
2022-06-20 10:15:31 -07:00
RISCVInstrFormats.td
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp
[Target, CodeGen] Use isImm(), isReg(), etc (NFC)
2022-06-18 07:41:04 -07:00
RISCVInstrInfo.h
[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
2022-06-12 10:47:21 -07:00
RISCVInstrInfo.td
[RISCV] Add RISCVISD opcodes for the rest of get*Addr.
2022-06-22 09:21:07 -07:00
RISCVInstrInfoA.td
[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
2022-06-03 09:00:17 -07:00
RISCVInstrInfoC.td
[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoF.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoM.td
[RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL
2022-04-25 10:53:41 -07:00
RISCVInstrInfoV.td
[RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
2022-03-31 01:33:17 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove true_mask patterns for VRGATHERE16..
2022-06-21 11:59:37 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Replace uses of VLOpFrag in VLMax patterns with srcvalue.
2022-06-14 19:19:35 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Move the passthru operand for RISCVISD::VRGATHER*_VL nodes. NFC
2022-06-21 14:01:02 -07:00
RISCVInstrInfoZb.td
[RISCV] Use isShiftedInt to improve readability. NFC
2022-06-12 21:04:45 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
2022-06-12 10:47:21 -07:00
RISCVMachineFunctionInfo.cpp
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMachineFunctionInfo.h
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMacroFusion.cpp
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Add pre-emit pass to make more instructions compressible
2022-05-25 09:25:02 +01:00
RISCVMergeBaseOffset.cpp
[Target, CodeGen] Use isImm(), isReg(), etc (NFC)
2022-06-18 07:41:04 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
2022-06-12 10:47:21 -07:00
RISCVRegisterInfo.h
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td
[RISCV] Add llvm.read.register support for vlenb
2022-05-13 09:12:02 -07:00
RISCVSExtWRemoval.cpp
[RISCV] transform MI to W variant to remove sext.w
2022-04-22 10:59:26 -07:00
RISCVSchedRocket.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedule.td
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RISCVScheduleB.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVScheduleV.td
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RISCVSubtarget.cpp
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVSubtarget.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVTargetMachine.h
[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
2022-04-08 11:55:48 +08:00
RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[RISCV] Fix crash when costing scalable gather/scatter of pointer
2022-06-20 12:50:42 -07:00
RISCVTargetTransformInfo.h
[RISCV] Implement isElementTypeLegalForScalableVector TTI hook
2022-06-10 13:20:58 -07:00
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