llvm-project/llvm/lib/Target/Sparc
Rainer Orth 09c1ee1086 [Sparc] Don't claim JIT support on SPARC for now
Until D118450 <https://reviews.llvm.org/D118450> lands, there's no JIT
support on SPARC, but the backend claims otherwise, leading to various
testsuite failures.

This patch corrects this.

Tested on `sparcv9-sun-solaris2.11`.

Differential Revision: https://reviews.llvm.org/D129349
2022-07-15 08:18:40 +02:00
..
AsmParser Fix "not all control paths return a value" MSVC warning. NFC. 2022-06-06 11:31:46 +01:00
Disassembler [MCDisassembler] Disambiguate Size parameter in tryAddingSymbolicOperand() 2022-05-25 13:44:32 -07:00
MCTargetDesc [CodeGen] Move instruction predicate verification to emitInstruction 2022-07-14 09:33:28 +01:00
TargetInfo [Sparc] Don't claim JIT support on SPARC for now 2022-07-15 08:18:40 +02:00
CMakeLists.txt [Sparc] Don't claim JIT support on SPARC for now 2022-07-15 08:18:40 +02:00
DelaySlotFiller.cpp [Sparc] Add tail call support 2022-03-08 13:50:54 +01:00
LeonFeatures.td
LeonPasses.cpp
LeonPasses.h
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp [CodeGen] Move instruction predicate verification to emitInstruction 2022-07-14 09:33:28 +01:00
SparcCallingConv.td [Sparc] Add tail call support 2022-03-08 13:50:54 +01:00
SparcFrameLowering.cpp [SPARC] Don't do leaf optimization on procedures with inline assembly 2022-06-27 15:09:30 +02:00
SparcFrameLowering.h
SparcISelDAGToDAG.cpp [NFC] Use Register instead of unsigned 2022-01-19 20:17:04 +08:00
SparcISelLowering.cpp [SPARC][MC] Support more relocation types 2022-06-05 14:09:39 -04:00
SparcISelLowering.h [SPARC][MC] Support more relocation types 2022-06-05 14:09:39 -04:00
SparcInstr64Bit.td [SPARC][MC] Support more relocation types 2022-06-05 14:09:39 -04:00
SparcInstrAliases.td
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td [SPARC][MC] Support more relocation types 2022-06-05 14:09:39 -04:00
SparcInstrVIS.td
SparcMCInstLower.cpp
SparcMachineFunctionInfo.cpp llvm-reduce: Add cloning of target MachineFunctionInfo 2022-06-07 10:14:48 -04:00
SparcMachineFunctionInfo.h llvm-reduce: Add cloning of target MachineFunctionInfo 2022-06-07 10:14:48 -04:00
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSchedule.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetMachine.cpp [llvm] Use value_or instead of getValueOr (NFC) 2022-06-18 23:07:11 -07:00
SparcTargetMachine.h
SparcTargetObjectFile.cpp
SparcTargetObjectFile.h [llvm] Use = default (NFC) 2022-02-06 22:18:35 -08:00

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.