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AsmParser
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[RISCV][CodeGen] add assertion to RISCVTargetStreamer getTargetStreamer()
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2022-08-31 11:15:47 -07:00 |
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Disassembler
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[RISCV] Implement assembler support for XVentanaCondOps
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2022-11-14 09:01:54 -08:00 |
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MCTargetDesc
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[NFC][RISCV] Move getSEWLMULRatio function to header
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2022-10-05 15:10:53 +01:00 |
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TargetInfo
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[RISCV] Re-enable JIT support
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2022-08-11 11:41:02 +02:00 |
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CMakeLists.txt
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[RISCV] Add a RISCV specific CodeGenPrepare pass.
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2022-07-14 10:20:59 -07:00 |
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RISCV.h
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[RISCV] Pre-RA expand pseudos pass
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2022-07-31 23:19:00 +02:00 |
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RISCV.td
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[RISCV] Implement assembler support for XVentanaCondOps
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2022-11-14 09:01:54 -08:00 |
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RISCVAsmPrinter.cpp
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[RISC-V][HWASAN] Fold variable into assert
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2022-08-29 00:32:37 +02:00 |
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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…
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RISCVCallingConv.td
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…
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RISCVCodeGenPrepare.cpp
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[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
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2022-08-12 22:21:05 -07:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
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2022-08-17 13:49:15 +01:00 |
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RISCVExpandPseudoInsts.cpp
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[RISCV] Add basic support for the sifive-7-series short forward branch optimization.
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2022-10-17 13:56:22 -07:00 |
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RISCVFrameLowering.cpp
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[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
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2022-10-20 14:05:46 -07:00 |
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RISCVFrameLowering.h
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Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"
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2022-11-01 20:04:07 -07:00 |
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RISCVGatherScatterLowering.cpp
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[RISCV] Extend strided load/store pattern matching to non-loop cases
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2022-09-27 12:56:58 -07:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Add PACKH/PACKW/PACK to hasAllNBitUsers.
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2022-11-13 23:57:52 -08:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Improve selection of PACK/PACKW for AssertZExt input.
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2022-11-13 16:00:45 -08:00 |
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RISCVISelLowering.cpp
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[RISCV] Teach shouldSinkOperands that vp.add and friends are commutative.
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2022-11-14 22:01:59 -08:00 |
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RISCVISelLowering.h
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[RISCV] Expand i32 abs to negw+max at isel.
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2022-11-14 19:44:05 -08:00 |
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RISCVInsertVSETVLI.cpp
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[RISCV] Map pseudos to their BaseInstr to reduce cases
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2022-10-27 16:50:15 +08:00 |
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RISCVInstrFormats.td
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[RISCV] Define custom-N opcodes
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2022-11-04 10:05:30 -07:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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[RISCV] Use OPCFG format record for vsetvli in tablgen. NFC
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2022-11-10 21:08:07 -08:00 |
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RISCVInstrInfo.cpp
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[MachineCombiner][RISCV] Enable MachineCombiner for RISCV
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2022-10-18 18:56:32 +03:00 |
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RISCVInstrInfo.h
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[MachineCombiner][RISCV] Enable MachineCombiner for RISCV
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2022-10-18 18:56:32 +03:00 |
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RISCVInstrInfo.td
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[RISCV] Implement assembler support for XVentanaCondOps
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2022-11-14 09:01:54 -08:00 |
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RISCVInstrInfoA.td
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[RISCV] Add target feature to force-enable atomics
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2022-08-09 16:04:46 +02:00 |
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RISCVInstrInfoC.td
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[RISCV] : Add support for simm10_lsb0000nonzero operand.
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2022-08-26 14:37:37 +08:00 |
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RISCVInstrInfoD.td
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[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
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2022-10-26 14:36:49 -07:00 |
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RISCVInstrInfoF.td
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[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
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2022-10-26 14:36:49 -07:00 |
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RISCVInstrInfoM.td
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[RISCV][Clang] Add support for Zmmul extension
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2022-07-18 20:26:08 -04:00 |
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RISCVInstrInfoV.td
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[RISCV][CodeGen] Account for LMUL for Vector Integer Arithmetic Instructions
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2022-11-03 09:18:42 -07:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV][CodeGen] Account for LMUL for Vector Integer Arithmetic Instructions
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2022-11-03 09:18:42 -07:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber.
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2022-10-03 21:44:08 -07:00 |
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RISCVInstrInfoVVLPatterns.td
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[VP][RISCV] Add vp.rint and RISC-V support.
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2022-11-01 14:52:47 +08:00 |
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RISCVInstrInfoXVentana.td
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[RISCV] Implement assembler support for XVentanaCondOps
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2022-11-14 09:01:54 -08:00 |
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RISCVInstrInfoZb.td
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[RISCV] Expand i32 abs to negw+max at isel.
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2022-11-14 19:44:05 -08:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
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2022-10-26 14:36:49 -07:00 |
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RISCVInstrInfoZicbo.td
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[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
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2022-09-01 13:49:55 +01:00 |
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RISCVInstrInfoZk.td
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RISCVInstructionSelector.cpp
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
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[RISCV] Pre-RA expand pseudos pass
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2022-07-31 23:19:00 +02:00 |
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RISCVMachineFunctionInfo.cpp
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[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
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2022-10-04 15:39:10 -07:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
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2022-10-04 15:39:10 -07:00 |
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RISCVMacroFusion.cpp
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[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
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2022-08-21 10:58:15 -07:00 |
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RISCVMacroFusion.h
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[RISCV] Add macrofusion infrastructure and one example usage.
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2022-06-23 08:38:39 -07:00 |
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RISCVMakeCompressible.cpp
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[RISCV] Fix wrong register rename for store value during make-compressible optimization
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2022-07-08 18:07:17 +08:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Fix operand number in debug message in RISCVMergeBaseOffset.
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2022-08-02 15:27:23 -07:00 |
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RISCVRedundantCopyElimination.cpp
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[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
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2022-08-29 09:05:53 -07:00 |
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RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"
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2022-11-01 20:04:07 -07:00 |
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RISCVRegisterInfo.h
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Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"
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2022-11-01 20:04:07 -07:00 |
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RISCVRegisterInfo.td
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[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
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2022-08-24 14:16:20 +00:00 |
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RISCVSExtWRemoval.cpp
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[RISCV] Add PseudoCCMOVGPR to RISCVSExtWRemoval.
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2022-11-14 13:39:00 -08:00 |
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RISCVSchedRocket.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVSchedSiFive7.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVSchedule.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVScheduleV.td
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[RISCV][CodeGen] Account for LMUL for Vector Integer Arithmetic Instructions
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2022-11-03 09:18:42 -07:00 |
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RISCVScheduleZb.td
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[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
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2022-09-23 21:38:42 -07:00 |
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RISCVSubtarget.cpp
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[RISCV] Enable fixed length vectors and loop vectorization with same
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2022-08-26 14:45:23 -07:00 |
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RISCVSubtarget.h
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[RISCV] Implement assembler support for XVentanaCondOps
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2022-11-14 09:01:54 -08:00 |
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RISCVSystemOperands.td
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RISCVTargetMachine.cpp
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[RISCV] Adjust RV64I data layout by using n32:64 in layout string
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2022-10-28 08:27:03 -07:00 |
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RISCVTargetMachine.h
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[llvm] Remove redundaunt virtual specifiers (NFC)
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2022-07-24 21:50:35 -07:00 |
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Prevent autovectorization using vscale with Zvl32b.
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2022-11-02 13:55:21 -07:00 |
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RISCVTargetTransformInfo.h
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[LV][RISCV] Disable vectorization of epilogue loops
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2022-10-25 14:28:02 -07:00 |
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