95 lines
5.1 KiB
C++
95 lines
5.1 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Check that the PowerPC vector registers are restored properly during
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// unwinding. Option -mabi=vec-extabi is required to compile the test case.
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// REQUIRES: target=powerpc{{(64)?}}-ibm-aix
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// ADDITIONAL_COMPILE_FLAGS: -mabi=vec-extabi
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// UNSUPPORTED: no-exceptions
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// AIX does not support the eh_frame section. Instead, the traceback table
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// located at the end of each function provides the information for stack
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// unwinding. Non-volatile GRs, FRs, and VRs clobbered by the function are
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// saved on the stack and the numbers of saved registers are available in the
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// traceback table. Registers are saved from high number to low consecutively,
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// e.g., if n VRs are saved, the order on the stack will be VR31, VR30, ...,
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// VR31-n+1. This test cases checks the unwinder gets to the location of saved
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// VRs which should be 16-byte aligned and restores them correctly based on
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// the number specified in the traceback table. To simplify, only the 2 high
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// numbered VRs are checked. Because PowerPC CPUs do not have instructions to
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// assign a literal value to a VR directly until Power10, and the instructions
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// to assign to a VR from a GR and vice versa are not available until Power8,
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// vector instructions available on Power7 are used to facilitate the test
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// so that it can run on all supported PowerPC architectures. In the code
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// below, VR31 is equivalent to VS63, VR30 is equivalent to VS62 (see PowerPC
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// documents for details).
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//
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#include <cstdlib>
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#include <cassert>
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int __attribute__((noinline)) test2(int i)
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{
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if (i > 3)
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throw i;
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srand(i);
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return rand();
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}
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int __attribute__((noinline)) test(int i) {
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// Clobber VS63 and VS62 in the function body.
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// Set VS63 to 16 bytes each with value 9
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asm volatile("vspltisb 31, 9" : : : "v31");
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// Set VS62 to 16 bytes each with value 12
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asm volatile("vspltisb 30, 12" : : : "v30");
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return test2(i);
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}
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#define cmpVS63(vec, result) \
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{ \
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vector unsigned char gbg; \
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asm volatile("vcmpequb. %[gbg], 31, %[veca];" \
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"mfocrf %[res], 2;" \
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"rlwinm %[res], %[res], 25, 31, 31" \
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: [res] "=r"(result), [gbg] "=v"(gbg) \
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: [veca] "v"(vec) \
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: "cr6"); \
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}
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#define cmpVS62(vec, result) \
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{ \
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vector unsigned char gbg; \
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asm volatile("vcmpequb. %[gbg], 30, %[veca];" \
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"mfocrf %[res], 2;" \
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"rlwinm %[res], %[res], 25, 31, 31" \
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: [res] "=r"(result), [gbg] "=v"(gbg) \
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: [veca] "v"(vec) \
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: "cr6"); \
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}
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int main(int, char**) {
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// Set VS63 to 16 bytes each with value 1
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asm volatile("vspltisb 31, 1" : : : "v31");
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// Set VS62 to 16 bytes each with value 2
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asm volatile("vspltisb 30, 2" : : : "v30");
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vector unsigned long long expectedVS63Value = {0x101010101010101, 0x101010101010101};
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vector unsigned long long expectedVS62Value = {0x202020202020202, 0x202020202020202};
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try {
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test(4);
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} catch (int num) {
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// If the unwinder restores VS63 and VS62 correctly, they should contain
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// 0x01's and 0x02's respectively instead of 0x09's and 0x12's.
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bool isEqualVS63, isEqualVS62;
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cmpVS63(expectedVS63Value, isEqualVS63);
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cmpVS62(expectedVS62Value, isEqualVS62);
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assert(isEqualVS63 && isEqualVS62);
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}
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return 0;
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}
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