llvm-project/llvm/test/CodeGen
Stefan Pintilie 1492c88f49 [PowerPC] Fix bugs in sign-/zero-extension elimination
This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass.
- Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer).
- Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension).

To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D40554
2022-08-19 07:05:40 -05:00
..
AArch64 [AArch64][GISel] Lower llvm.prefetch 2022-08-19 09:11:18 +01:00
AMDGPU [amdgpu] Change the RA to basic 2022-08-18 08:16:19 +08:00
ARC
ARM Untangle the mess which is MachineBasicBlock::hasAddressTaken(). 2022-08-16 16:15:44 -07:00
AVR [AVR] Only push and clear R1 in interrupts when necessary 2022-08-15 14:29:38 +02:00
BPF [Clang][BPF] Support record argument with direct values 2022-08-18 19:11:50 -07:00
CSKY [CSKY] Fix the btsti16 instruction missing in generic processor 2022-07-27 17:39:15 +08:00
DirectX
Generic [VP] IR expansion pass for VP gather and scatter 2022-07-18 17:00:38 +02:00
Hexagon Untangle the mess which is MachineBasicBlock::hasAddressTaken(). 2022-08-16 16:15:44 -07:00
Inputs
Lanai
LoongArch [LoongArch] Supports brcond with 21 bit offsets 2022-08-18 15:55:50 +08:00
M68k [M68k] Add MC support for link/unlk 2022-08-08 11:00:11 +08:00
MIR Untangle the mess which is MachineBasicBlock::hasAddressTaken(). 2022-08-16 16:15:44 -07:00
MLRegalloc
MSP430
Mips [DAG] SimplifyDemandedBits - relax "xor (X >> ShiftC), XorC --> (not X) >> ShiftC" to match only demanded bits 2022-07-19 10:59:07 +01:00
NVPTX [NVPTX] Promote i24, i40, i48 and i56 to next power-of-two register when passing 2022-07-22 14:14:12 -07:00
PowerPC [PowerPC] Fix bugs in sign-/zero-extension elimination 2022-08-19 07:05:40 -05:00
RISCV [IR] Update llvm.prefetch to match docs 2022-08-19 09:11:17 +01:00
SPARC [Sparc] Don't use SunStyleELFSectionSwitchSyntax 2022-08-17 12:59:29 +02:00
SPIRV [SPIRV] support capabilities and extensions 2022-08-12 23:33:15 +03:00
SystemZ Migrate llvm.experimental.patchpoint() to ptr. 2022-08-10 13:18:02 +01:00
Thumb
Thumb2 Revert "[ModuloSchedule] Add interface call to accept/reject SMS schedules" 2022-08-17 09:32:43 -07:00
VE [NFC] Automatically generate CodeGen/VE/Scalar/atomic.ll 2022-07-27 23:52:00 +00:00
WebAssembly [WebAssembly] WebAssemblyLowerEmscriptenEHSjLj: Fix signature of malloc in wasm64 mode 2022-08-17 18:16:34 -07:00
WinCFGuard
WinEH
X86 RAGreedyStats: Ignore identity COPYs; count COPYs from/to physregs 2022-08-17 12:53:29 -07:00
XCore