357 lines
13 KiB
LLVM
357 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) #0 {
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; CHECK-LABEL: select_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: adrp x9, .LCPI0_1
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; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI0_1]
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; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h
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; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <4 x i1> %mask, <4 x i8> %op1, <4 x i8> %op2
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ret <4 x i8> %sel
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}
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define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {
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; CHECK-LABEL: select_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: adrp x9, .LCPI1_1
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; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
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; CHECK-NEXT: ptrue p0.b, vl8
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI1_1]
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; CHECK-NEXT: lsl z2.b, p0/m, z2.b, z3.b
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; CHECK-NEXT: asr z2.b, p0/m, z2.b, z3.b
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <8 x i1> %mask, <8 x i8> %op1, <8 x i8> %op2
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ret <8 x i8> %sel
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}
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define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) #0 {
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; CHECK-LABEL: select_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI2_0
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; CHECK-NEXT: adrp x9, .LCPI2_1
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; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI2_0]
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; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI2_1]
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; CHECK-NEXT: lsl z2.b, p0/m, z2.b, z3.b
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; CHECK-NEXT: asr z2.b, p0/m, z2.b, z3.b
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <16 x i1> %mask, <16 x i8> %op1, <16 x i8> %op2
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ret <16 x i8> %sel
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}
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define void @select_v32i8(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: select_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x1]
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: ldp q3, q2, [x0]
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z0.b
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; CHECK-NEXT: cmpeq p0.b, p0/z, z3.b, z1.b
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; CHECK-NEXT: mov z5.b, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z6.b, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: eor z5.d, z5.d, z4.d
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; CHECK-NEXT: eor z4.d, z6.d, z4.d
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; CHECK-NEXT: and z3.d, z3.d, z6.d
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; CHECK-NEXT: and z1.d, z1.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z5.d
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; CHECK-NEXT: orr z1.d, z3.d, z1.d
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; CHECK-NEXT: orr z0.d, z2.d, z0.d
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; CHECK-NEXT: stp q1, q0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x i8>, ptr %a
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%op2 = load <32 x i8>, ptr %b
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%mask = icmp eq <32 x i8> %op1, %op2
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%sel = select <32 x i1> %mask, <32 x i8> %op1, <32 x i8> %op2
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store <32 x i8> %sel, ptr %a
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ret void
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}
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define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) #0 {
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; CHECK-LABEL: select_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI4_0
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; CHECK-NEXT: adrp x9, .LCPI4_1
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; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI4_0]
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; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI4_1]
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; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <2 x i1> %mask, <2 x i16> %op1, <2 x i16> %op2
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ret <2 x i16> %sel
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}
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define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) #0 {
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; CHECK-LABEL: select_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI5_0
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; CHECK-NEXT: adrp x9, .LCPI5_1
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; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI5_0]
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; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI5_1]
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; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h
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; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <4 x i1> %mask, <4 x i16> %op1, <4 x i16> %op2
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ret <4 x i16> %sel
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}
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define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #0 {
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; CHECK-LABEL: select_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI6_0
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; CHECK-NEXT: adrp x9, .LCPI6_1
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; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: uunpklo z2.h, z2.b
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI6_0]
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; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI6_1]
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; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h
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; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <8 x i1> %mask, <8 x i16> %op1, <8 x i16> %op2
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ret <8 x i16> %sel
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}
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define void @select_v16i16(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: select_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x1]
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; CHECK-NEXT: adrp x8, .LCPI7_0
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: ldp q3, q2, [x0]
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI7_0]
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; CHECK-NEXT: cmpeq p1.h, p0/z, z2.h, z0.h
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; CHECK-NEXT: cmpeq p0.h, p0/z, z3.h, z1.h
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; CHECK-NEXT: mov z5.h, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z6.h, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: eor z5.d, z5.d, z4.d
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; CHECK-NEXT: eor z4.d, z6.d, z4.d
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; CHECK-NEXT: and z3.d, z3.d, z6.d
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; CHECK-NEXT: and z1.d, z1.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z5.d
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; CHECK-NEXT: orr z1.d, z3.d, z1.d
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; CHECK-NEXT: orr z0.d, z2.d, z0.d
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; CHECK-NEXT: stp q1, q0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i16>, ptr %a
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%op2 = load <16 x i16>, ptr %b
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%mask = icmp eq <16 x i16> %op1, %op2
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%sel = select <16 x i1> %mask, <16 x i16> %op1, <16 x i16> %op2
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store <16 x i16> %sel, ptr %a
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ret void
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}
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define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #0 {
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; CHECK-LABEL: select_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI8_0
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; CHECK-NEXT: adrp x9, .LCPI8_1
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; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI8_0]
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; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI8_1]
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; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <2 x i1> %mask, <2 x i32> %op1, <2 x i32> %op2
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ret <2 x i32> %sel
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}
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define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #0 {
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; CHECK-LABEL: select_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI9_0
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; CHECK-NEXT: adrp x9, .LCPI9_1
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; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: uunpklo z2.s, z2.h
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI9_0]
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; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI9_1]
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; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <4 x i1> %mask, <4 x i32> %op1, <4 x i32> %op2
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ret <4 x i32> %sel
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}
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define void @select_v8i32(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: select_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x1]
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; CHECK-NEXT: adrp x8, .LCPI10_0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: ldp q3, q2, [x0]
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI10_0]
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; CHECK-NEXT: cmpeq p1.s, p0/z, z2.s, z0.s
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; CHECK-NEXT: cmpeq p0.s, p0/z, z3.s, z1.s
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; CHECK-NEXT: mov z5.s, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: mov z6.s, p0/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: eor z5.d, z5.d, z4.d
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; CHECK-NEXT: eor z4.d, z6.d, z4.d
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; CHECK-NEXT: and z3.d, z3.d, z6.d
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; CHECK-NEXT: and z1.d, z1.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z5.d
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; CHECK-NEXT: orr z1.d, z3.d, z1.d
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; CHECK-NEXT: orr z0.d, z2.d, z0.d
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; CHECK-NEXT: stp q1, q0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x i32>, ptr %a
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%op2 = load <8 x i32>, ptr %b
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%mask = icmp eq <8 x i32> %op1, %op2
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%sel = select <8 x i1> %mask, <8 x i32> %op1, <8 x i32> %op2
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store <8 x i32> %sel, ptr %a
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ret void
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}
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define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #0 {
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; CHECK-LABEL: select_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: mov x9, #-1
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; CHECK-NEXT: csetm x8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: fmov d3, x9
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; CHECK-NEXT: fmov d2, x8
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%sel = select <1 x i1> %mask, <1 x i64> %op1, <1 x i64> %op2
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ret <1 x i64> %sel
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}
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define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #0 {
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; CHECK-LABEL: select_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI12_0
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; CHECK-NEXT: adrp x9, .LCPI12_1
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; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: uunpklo z2.d, z2.s
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI12_0]
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; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI12_1]
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; CHECK-NEXT: lsl z2.d, p0/m, z2.d, z3.d
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; CHECK-NEXT: asr z2.d, p0/m, z2.d, z3.d
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; CHECK-NEXT: eor z3.d, z2.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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|
; CHECK-NEXT: ret
|
|
%sel = select <2 x i1> %mask, <2 x i64> %op1, <2 x i64> %op2
|
|
ret <2 x i64> %sel
|
|
}
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|
|
|
define void @select_v4i64(ptr %a, ptr %b) #0 {
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|
; CHECK-LABEL: select_v4i64:
|
|
; CHECK: // %bb.0:
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|
; CHECK-NEXT: ldp q1, q0, [x1]
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|
; CHECK-NEXT: adrp x8, .LCPI13_0
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|
; CHECK-NEXT: ptrue p0.d, vl2
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|
; CHECK-NEXT: ldp q3, q2, [x0]
|
|
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI13_0]
|
|
; CHECK-NEXT: cmpeq p1.d, p0/z, z2.d, z0.d
|
|
; CHECK-NEXT: cmpeq p0.d, p0/z, z3.d, z1.d
|
|
; CHECK-NEXT: mov z5.d, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: mov z6.d, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: and z2.d, z2.d, z5.d
|
|
; CHECK-NEXT: eor z5.d, z5.d, z4.d
|
|
; CHECK-NEXT: eor z4.d, z6.d, z4.d
|
|
; CHECK-NEXT: and z3.d, z3.d, z6.d
|
|
; CHECK-NEXT: and z1.d, z1.d, z4.d
|
|
; CHECK-NEXT: and z0.d, z0.d, z5.d
|
|
; CHECK-NEXT: orr z1.d, z3.d, z1.d
|
|
; CHECK-NEXT: orr z0.d, z2.d, z0.d
|
|
; CHECK-NEXT: stp q1, q0, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x i64>, ptr %a
|
|
%op2 = load <4 x i64>, ptr %b
|
|
%mask = icmp eq <4 x i64> %op1, %op2
|
|
%sel = select <4 x i1> %mask, <4 x i64> %op1, <4 x i64> %op2
|
|
store <4 x i64> %sel, ptr %a
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" uwtable }
|