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[Target] Use range-based for loops (NFC)

This commit is contained in:
Kazu Hirata 2021-12-17 10:11:08 -08:00
parent 4c9e31a481
commit f78c1b07cb
5 changed files with 47 additions and 66 deletions
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42
llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
View File

@ -150,19 +150,18 @@ bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned>> &Remap)
const {
unsigned CurrentUndexIdx = 0;
for (DenseMap<Register, unsigned>::iterator It = ToMerge->RegToChan.begin(),
E = ToMerge->RegToChan.end(); It != E; ++It) {
for (auto &It : ToMerge->RegToChan) {
DenseMap<Register, unsigned>::const_iterator PosInUntouched =
Untouched->RegToChan.find((*It).first);
Untouched->RegToChan.find(It.first);
if (PosInUntouched != Untouched->RegToChan.end()) {
Remap.push_back(std::pair<unsigned, unsigned>
((*It).second, (*PosInUntouched).second));
Remap.push_back(
std::pair<unsigned, unsigned>(It.second, (*PosInUntouched).second));
continue;
}
if (CurrentUndexIdx >= Untouched->UndefReg.size())
return false;
Remap.push_back(std::pair<unsigned, unsigned>
((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
Remap.push_back(std::pair<unsigned, unsigned>(
It.second, Untouched->UndefReg[CurrentUndexIdx++]));
}
return true;
@ -172,9 +171,9 @@ static
unsigned getReassignedChan(
const std::vector<std::pair<unsigned, unsigned>> &RemapChan,
unsigned Chan) {
for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
if (RemapChan[j].first == Chan)
return RemapChan[j].second;
for (const auto &J : RemapChan) {
if (J.first == Chan)
return J.second;
}
llvm_unreachable("Chan wasn't reassigned");
}
@ -190,11 +189,10 @@ MachineInstr *R600VectorRegMerger::RebuildVector(
Register SrcVec = BaseRSI->Instr->getOperand(0).getReg();
DenseMap<Register, unsigned> UpdatedRegToChan = BaseRSI->RegToChan;
std::vector<Register> UpdatedUndef = BaseRSI->UndefReg;
for (DenseMap<Register, unsigned>::iterator It = RSI->RegToChan.begin(),
E = RSI->RegToChan.end(); It != E; ++It) {
for (const auto &It : RSI->RegToChan) {
Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass);
unsigned SubReg = (*It).first;
unsigned Swizzle = (*It).second;
unsigned SubReg = It.first;
unsigned Swizzle = It.second;
unsigned Chan = getReassignedChan(RemapChan, Swizzle);
MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG),
@ -234,14 +232,12 @@ MachineInstr *R600VectorRegMerger::RebuildVector(
}
void R600VectorRegMerger::RemoveMI(MachineInstr *MI) {
for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(),
E = PreviousRegSeqByReg.end(); It != E; ++It) {
std::vector<MachineInstr *> &MIs = (*It).second;
for (auto &It : PreviousRegSeqByReg) {
std::vector<MachineInstr *> &MIs = It.second;
MIs.erase(llvm::find(MIs, MI), MIs.end());
}
for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(),
E = PreviousRegSeqByUndefCount.end(); It != E; ++It) {
std::vector<MachineInstr *> &MIs = (*It).second;
for (auto &It : PreviousRegSeqByUndefCount) {
std::vector<MachineInstr *> &MIs = It.second;
MIs.erase(llvm::find(MIs, MI), MIs.end());
}
}
@ -255,9 +251,9 @@ void R600VectorRegMerger::SwizzleInput(MachineInstr &MI,
Offset = 3;
for (unsigned i = 0; i < 4; i++) {
unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
for (unsigned j = 0, e = RemapChan.size(); j < e; j++) {
if (RemapChan[j].first == Swizzle) {
MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
for (const auto &J : RemapChan) {
if (J.first == Swizzle) {
MI.getOperand(i + Offset).setImm(J.second - 1);
break;
}
}

6
llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
View File

@ -54,10 +54,8 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
E = R600::R600_AddrRegClass.end(); I != E; ++I) {
reserveRegisterTuples(Reserved, *I);
}
for (MCPhysReg R : R600::R600_AddrRegClass)
reserveRegisterTuples(Reserved, R);
TII->reserveIndirectRegisters(Reserved, MF, *this);

3
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -5051,8 +5051,7 @@ void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
--ConstantBusLimit;
}
for (unsigned i = 0; i < 3; ++i) {
int Idx = VOP3Idx[i];
for (int Idx : VOP3Idx) {
if (Idx == -1)
break;
MachineOperand &MO = MI.getOperand(Idx);

53
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
View File

@ -869,29 +869,27 @@ void SIScheduleBlockCreator::colorComputeReservedDependencies() {
}
void SIScheduleBlockCreator::colorAccordingToReservedDependencies() {
unsigned DAGSize = DAG->SUnits.size();
std::map<std::pair<unsigned, unsigned>, unsigned> ColorCombinations;
// Every combination of colors given by the top down
// and bottom up Reserved node dependency
for (unsigned i = 0, e = DAGSize; i != e; ++i) {
SUnit *SU = &DAG->SUnits[i];
for (const SUnit &SU : DAG->SUnits) {
std::pair<unsigned, unsigned> SUColors;
// High latency instructions: already given.
if (CurrentColoring[SU->NodeNum])
if (CurrentColoring[SU.NodeNum])
continue;
SUColors.first = CurrentTopDownReservedDependencyColoring[SU->NodeNum];
SUColors.second = CurrentBottomUpReservedDependencyColoring[SU->NodeNum];
SUColors.first = CurrentTopDownReservedDependencyColoring[SU.NodeNum];
SUColors.second = CurrentBottomUpReservedDependencyColoring[SU.NodeNum];
std::map<std::pair<unsigned, unsigned>, unsigned>::iterator Pos =
ColorCombinations.find(SUColors);
if (Pos != ColorCombinations.end()) {
CurrentColoring[SU->NodeNum] = Pos->second;
CurrentColoring[SU.NodeNum] = Pos->second;
} else {
CurrentColoring[SU->NodeNum] = NextNonReservedID;
CurrentColoring[SU.NodeNum] = NextNonReservedID;
ColorCombinations[SUColors] = NextNonReservedID++;
}
}
@ -1232,15 +1230,13 @@ void SIScheduleBlockCreator::createBlocksForVariant(SISchedulerBlockCreatorVaria
}
// Free root and leafs of all blocks to enable scheduling inside them.
for (unsigned i = 0, e = CurrentBlocks.size(); i != e; ++i) {
SIScheduleBlock *Block = CurrentBlocks[i];
for (SIScheduleBlock *Block : CurrentBlocks)
Block->finalizeUnits();
}
LLVM_DEBUG(dbgs() << "Blocks created:\n\n";
for (unsigned i = 0, e = CurrentBlocks.size(); i != e; ++i) {
SIScheduleBlock *Block = CurrentBlocks[i];
Block->printDebug(true);
});
LLVM_DEBUG({
dbgs() << "Blocks created:\n\n";
for (SIScheduleBlock *Block : CurrentBlocks)
Block->printDebug(true);
});
}
// Two functions taken from Codegen/MachineScheduler.cpp
@ -1379,9 +1375,9 @@ void SIScheduleBlockCreator::scheduleInsideBlocks() {
}
}
LLVM_DEBUG(for (unsigned i = 0, e = CurrentBlocks.size(); i != e; ++i) {
SIScheduleBlock *Block = CurrentBlocks[i];
Block->printDebug(true);
LLVM_DEBUG({
for (SIScheduleBlock *Block : CurrentBlocks)
Block->printDebug(true);
});
}
@ -1437,8 +1433,7 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
// found for several parents, we increment the usage of the one with the
// highest topological index.
LiveOutRegsNumUsages.resize(Blocks.size());
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
SIScheduleBlock *Block = Blocks[i];
for (SIScheduleBlock *Block : Blocks) {
for (unsigned Reg : Block->getInRegs()) {
bool Found = false;
int topoInd = -1;
@ -1502,8 +1497,7 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
// Fill LiveRegsConsumers for regs that were already
// defined before scheduling.
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
SIScheduleBlock *Block = Blocks[i];
for (SIScheduleBlock *Block : Blocks) {
for (unsigned Reg : Block->getInRegs()) {
bool Found = false;
for (SIScheduleBlock* Pred: Block->getPreds()) {
@ -1700,10 +1694,7 @@ void SIScheduleBlockScheduler::blockScheduled(SIScheduleBlock *Block) {
decreaseLiveRegs(Block, Block->getInRegs());
addLiveRegs(Block->getOutRegs());
releaseBlockSuccs(Block);
for (std::map<unsigned, unsigned>::iterator RegI =
LiveOutRegsNumUsages[Block->getID()].begin(),
E = LiveOutRegsNumUsages[Block->getID()].end(); RegI != E; ++RegI) {
std::pair<unsigned, unsigned> RegP = *RegI;
for (const auto &RegP : LiveOutRegsNumUsages[Block->getID()]) {
// We produce this register, thus it must not be previously alive.
assert(LiveRegsConsumers.find(RegP.first) == LiveRegsConsumers.end() ||
LiveRegsConsumers[RegP.first] == 0);
@ -1759,8 +1750,7 @@ SIScheduler::scheduleVariant(SISchedulerBlockCreatorVariant BlockVariant,
ScheduledBlocks = Scheduler.getBlocks();
for (unsigned b = 0; b < ScheduledBlocks.size(); ++b) {
SIScheduleBlock *Block = ScheduledBlocks[b];
for (SIScheduleBlock *Block : ScheduledBlocks) {
std::vector<SUnit*> SUs = Block->getScheduledUnits();
for (SUnit* SU : SUs)
@ -2000,9 +1990,8 @@ void SIScheduleDAGMI::schedule()
assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
TopRPTracker.setPos(CurrentTop);
for (std::vector<unsigned>::iterator I = ScheduledSUnits.begin(),
E = ScheduledSUnits.end(); I != E; ++I) {
SUnit *SU = &SUnits[*I];
for (unsigned I : ScheduledSUnits) {
SUnit *SU = &SUnits[I];
scheduleMI(SU, true);

9
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
View File

@ -495,11 +495,10 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
// instruction as needing e.g. WQM before visiting it and realizing it needs
// WQM disabled.
ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
for (auto BI = RPOT.begin(), BE = RPOT.end(); BI != BE; ++BI) {
MachineBasicBlock &MBB = **BI;
BlockInfo &BBI = Blocks[&MBB];
for (MachineBasicBlock *MBB : RPOT) {
BlockInfo &BBI = Blocks[MBB];
for (MachineInstr &MI : MBB) {
for (MachineInstr &MI : *MBB) {
InstrInfo &III = Instructions[&MI];
unsigned Opcode = MI.getOpcode();
char Flags = 0;
@ -561,7 +560,7 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
BBI.Needs |= StateExact;
if (!(BBI.InNeeds & StateExact)) {
BBI.InNeeds |= StateExact;
Worklist.push_back(&MBB);
Worklist.push_back(MBB);
}
GlobalFlags |= StateExact;
III.Disabled = StateWQM | StateStrict;