[RISCV] Add more patterns for FNMADD
D54205 handles fnmadd: -rs1 * rs2 - rs3 This patch add fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D126852
This commit is contained in:
LiaoChunyu
parent
7c63cc198b
commit
f14d18c7a9
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@ -294,6 +294,10 @@ def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
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def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
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(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
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def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)),
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(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
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// LLVM's fminnum and fmaxnum.
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// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
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@ -53,6 +53,10 @@ def riscv_any_fcvt_wu_rv64 : PatFrags<(ops node:$src, node:$frm),
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[(riscv_strict_fcvt_wu_rv64 node:$src, node:$frm),
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(riscv_fcvt_wu_rv64 node:$src, node:$frm)]>;
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def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3),
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(any_fma node:$rs1, node:$rs2, node:$rs3), [{
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return N->getFlags().hasNoSignedZeros();
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}]>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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@ -520,6 +524,10 @@ def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
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def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
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(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
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// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
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def : Pat<(fneg (any_fma_nsz FPR32:$rs1, FPR32:$rs2, FPR32:$rs3)),
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(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
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// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
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// LLVM's fminnum and fmaxnum
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// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
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@ -296,6 +296,10 @@ def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3),
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def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
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(FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
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// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
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def : Pat<(fneg (any_fma_nsz FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)),
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(FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
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// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
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// LLVM's fminnum and fmaxnum
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// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
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@ -723,6 +723,85 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
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ret double %1
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}
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define double @fnmadd_d_3(double %a, double %b, double %c) nounwind {
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; RV32IFD-LABEL: fnmadd_d_3:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: fmadd.d ft0, fa0, fa1, fa2
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; RV32IFD-NEXT: fneg.d fa0, ft0
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fnmadd_d_3:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmadd.d ft0, fa0, fa1, fa2
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; RV64IFD-NEXT: fneg.d fa0, ft0
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; RV64IFD-NEXT: ret
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;
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; RV32I-LABEL: fnmadd_d_3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call fma@plt
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; RV32I-NEXT: lui a2, 524288
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fnmadd_d_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call fma@plt
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; RV64I-NEXT: li a1, -1
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; RV64I-NEXT: slli a1, a1, 63
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call double @llvm.fma.f64(double %a, double %b, double %c)
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%neg = fneg double %1
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ret double %neg
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}
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define double @fnmadd_nsz(double %a, double %b, double %c) nounwind {
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; RV32IFD-LABEL: fnmadd_nsz:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fnmadd_nsz:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
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; RV64IFD-NEXT: ret
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;
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; RV32I-LABEL: fnmadd_nsz:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call fma@plt
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; RV32I-NEXT: lui a2, 524288
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fnmadd_nsz:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call fma@plt
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; RV64I-NEXT: li a1, -1
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; RV64I-NEXT: slli a1, a1, 63
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call nsz double @llvm.fma.f64(double %a, double %b, double %c)
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%neg = fneg nsz double %1
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ret double %neg
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}
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define double @fnmsub_d(double %a, double %b, double %c) nounwind {
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; RV32IFD-LABEL: fnmsub_d:
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; RV32IFD: # %bb.0:
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@ -692,6 +692,82 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
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ret float %1
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}
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define float @fnmadd_s_3(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fnmadd_s_3:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmadd.s ft0, fa0, fa1, fa2
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; RV32IF-NEXT: fneg.s fa0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fnmadd_s_3:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmadd.s ft0, fa0, fa1, fa2
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; RV64IF-NEXT: fneg.s fa0, ft0
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: fnmadd_s_3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call fmaf@plt
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fnmadd_s_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call fmaf@plt
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; RV64I-NEXT: lui a1, 524288
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
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%neg = fneg float %1
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ret float %neg
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}
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define float @fnmadd_nsz(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fnmadd_nsz:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fnmadd_nsz:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: fnmadd_nsz:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call fmaf@plt
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fnmadd_nsz:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call fmaf@plt
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; RV64I-NEXT: lui a1, 524288
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call nsz float @llvm.fma.f32(float %a, float %b, float %c)
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%neg = fneg nsz float %1
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ret float %neg
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}
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define float @fnmsub_s(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fnmsub_s:
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; RV32IF: # %bb.0:
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@ -1240,6 +1240,179 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
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ret half %1
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}
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define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmadd_s_3:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmadd.h ft0, fa0, fa1, fa2
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; RV32IZFH-NEXT: fneg.h fa0, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmadd_s_3:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmadd.h ft0, fa0, fa1, fa2
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; RV64IZFH-NEXT: fneg.h fa0, ft0
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; RV64IZFH-NEXT: ret
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;
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; RV32I-LABEL: fnmadd_s_3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -32
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; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv s0, a2
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; RV32I-NEXT: mv s1, a1
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; RV32I-NEXT: lui a1, 16
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; RV32I-NEXT: addi s3, a1, -1
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; RV32I-NEXT: and a0, a0, s3
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; RV32I-NEXT: call __extendhfsf2@plt
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; RV32I-NEXT: mv s2, a0
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; RV32I-NEXT: and a0, s1, s3
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; RV32I-NEXT: call __extendhfsf2@plt
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; RV32I-NEXT: mv s1, a0
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; RV32I-NEXT: and a0, s0, s3
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; RV32I-NEXT: call __extendhfsf2@plt
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: mv a0, s2
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; RV32I-NEXT: mv a1, s1
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; RV32I-NEXT: call fmaf@plt
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; RV32I-NEXT: call __truncsfhf2@plt
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; RV32I-NEXT: lui a1, 1048568
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 32
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fnmadd_s_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -48
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; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: mv s0, a2
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; RV64I-NEXT: mv s1, a1
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; RV64I-NEXT: lui a1, 16
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; RV64I-NEXT: addiw s3, a1, -1
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; RV64I-NEXT: and a0, a0, s3
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; RV64I-NEXT: call __extendhfsf2@plt
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; RV64I-NEXT: mv s2, a0
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; RV64I-NEXT: and a0, s1, s3
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; RV64I-NEXT: call __extendhfsf2@plt
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; RV64I-NEXT: mv s1, a0
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; RV64I-NEXT: and a0, s0, s3
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; RV64I-NEXT: call __extendhfsf2@plt
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: mv a0, s2
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; RV64I-NEXT: mv a1, s1
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; RV64I-NEXT: call fmaf@plt
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; RV64I-NEXT: call __truncsfhf2@plt
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; RV64I-NEXT: lui a1, 1048568
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 48
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; RV64I-NEXT: ret
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%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
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%neg = fneg half %1
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ret half %neg
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}
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define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmadd_nsz:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmadd_nsz:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
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; RV64IZFH-NEXT: ret
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;
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; RV32I-LABEL: fnmadd_nsz:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -32
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; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv s0, a2
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; RV32I-NEXT: mv s1, a1
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; RV32I-NEXT: lui a1, 16
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||||
; RV32I-NEXT: addi s3, a1, -1
|
||||
; RV32I-NEXT: and a0, a0, s3
|
||||
; RV32I-NEXT: call __extendhfsf2@plt
|
||||
; RV32I-NEXT: mv s2, a0
|
||||
; RV32I-NEXT: and a0, s1, s3
|
||||
; RV32I-NEXT: call __extendhfsf2@plt
|
||||
; RV32I-NEXT: mv s1, a0
|
||||
; RV32I-NEXT: and a0, s0, s3
|
||||
; RV32I-NEXT: call __extendhfsf2@plt
|
||||
; RV32I-NEXT: mv a2, a0
|
||||
; RV32I-NEXT: mv a0, s2
|
||||
; RV32I-NEXT: mv a1, s1
|
||||
; RV32I-NEXT: call fmaf@plt
|
||||
; RV32I-NEXT: call __truncsfhf2@plt
|
||||
; RV32I-NEXT: lui a1, 1048568
|
||||
; RV32I-NEXT: xor a0, a0, a1
|
||||
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 32
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: fnmadd_nsz:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -48
|
||||
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: mv s0, a2
|
||||
; RV64I-NEXT: mv s1, a1
|
||||
; RV64I-NEXT: lui a1, 16
|
||||
; RV64I-NEXT: addiw s3, a1, -1
|
||||
; RV64I-NEXT: and a0, a0, s3
|
||||
; RV64I-NEXT: call __extendhfsf2@plt
|
||||
; RV64I-NEXT: mv s2, a0
|
||||
; RV64I-NEXT: and a0, s1, s3
|
||||
; RV64I-NEXT: call __extendhfsf2@plt
|
||||
; RV64I-NEXT: mv s1, a0
|
||||
; RV64I-NEXT: and a0, s0, s3
|
||||
; RV64I-NEXT: call __extendhfsf2@plt
|
||||
; RV64I-NEXT: mv a2, a0
|
||||
; RV64I-NEXT: mv a0, s2
|
||||
; RV64I-NEXT: mv a1, s1
|
||||
; RV64I-NEXT: call fmaf@plt
|
||||
; RV64I-NEXT: call __truncsfhf2@plt
|
||||
; RV64I-NEXT: lui a1, 1048568
|
||||
; RV64I-NEXT: xor a0, a0, a1
|
||||
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 48
|
||||
; RV64I-NEXT: ret
|
||||
%1 = call nsz half @llvm.fma.f16(half %a, half %b, half %c)
|
||||
%neg = fneg nsz half %1
|
||||
ret half %neg
|
||||
}
|
||||
|
||||
define half @fnmsub_s(half %a, half %b, half %c) nounwind {
|
||||
; RV32IZFH-LABEL: fnmsub_s:
|
||||
; RV32IZFH: # %bb.0:
|
||||
|
|
|
|||
Loading…
Reference in New Issue