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[AMDGPU] Assume getDefIgnoringCopies will succeed. NFC. 

getDefIgnoringCopies and getSrcRegIgnoringCopies should not fail on
valid MIR, so don't bother to check for failure.

Differential Revision: https://reviews.llvm.org/D136238
This commit is contained in:
Jay Foad 2022-10-19 10:32:08 +01:00
parent 3883615906
commit ea09a426a9
2 changed files with 6 additions and 12 deletions
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3
llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
View File

@ -20,9 +20,6 @@ std::pair<Register, unsigned>
AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
GISelKnownBits *KnownBits) {
MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
if (!Def)
return std::make_pair(Reg, 0);
if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
unsigned Offset;
const MachineOperand &Op = Def->getOperand(1);

15
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -674,7 +674,7 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
// TODO: This should probably be a combine somewhere
// (build_vector $src0, undef) -> copy $src0
MachineInstr *Src1Def = getDefIgnoringCopies(Src1, *MRI);
if (Src1Def && Src1Def->getOpcode() == AMDGPU::G_IMPLICIT_DEF) {
if (Src1Def->getOpcode() == AMDGPU::G_IMPLICIT_DEF) {
MI.setDesc(TII.get(AMDGPU::COPY));
MI.removeOperand(2);
const auto &RC =
@ -1451,8 +1451,6 @@ bool AMDGPUInstructionSelector::selectDSGWSIntrinsic(MachineInstr &MI,
return false;
MachineInstr *OffsetDef = getDefIgnoringCopies(BaseOffset, *MRI);
assert(OffsetDef);
unsigned ImmOffset;
MachineBasicBlock *MBB = MI.getParent();
@ -3036,7 +3034,7 @@ bool AMDGPUInstructionSelector::selectGlobalLoadLds(MachineInstr &MI) const{
} else if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
Register SAddr =
getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI);
if (SAddr && isSGPR(SAddr)) {
if (isSGPR(SAddr)) {
Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg();
if (Register Off = matchZeroExtendFromS32(*MRI, PtrBaseOffset)) {
Addr = SAddr;
@ -3330,13 +3328,13 @@ std::pair<Register, unsigned> AMDGPUInstructionSelector::selectVOP3ModsImpl(
unsigned Mods = 0;
MachineInstr *MI = getDefIgnoringCopies(Src, *MRI);
if (MI && MI->getOpcode() == AMDGPU::G_FNEG) {
if (MI->getOpcode() == AMDGPU::G_FNEG) {
Src = MI->getOperand(1).getReg();
Mods |= SISrcMods::NEG;
MI = getDefIgnoringCopies(Src, *MRI);
}
if (AllowAbs && MI && MI->getOpcode() == AMDGPU::G_FABS) {
if (AllowAbs && MI->getOpcode() == AMDGPU::G_FABS) {
Src = MI->getOperand(1).getReg();
Mods |= SISrcMods::ABS;
}
@ -3436,8 +3434,7 @@ InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVOP3NoMods(MachineOperand &Root) const {
Register Reg = Root.getReg();
const MachineInstr *Def = getDefIgnoringCopies(Reg, *MRI);
if (Def && (Def->getOpcode() == AMDGPU::G_FNEG ||
Def->getOpcode() == AMDGPU::G_FABS))
if (Def->getOpcode() == AMDGPU::G_FNEG || Def->getOpcode() == AMDGPU::G_FABS)
return {};
return {{
[=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); },
@ -3826,7 +3823,7 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const {
Register SAddr =
getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI);
if (SAddr && isSGPR(SAddr)) {
if (isSGPR(SAddr)) {
Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg();
// It's possible voffset is an SGPR here, but the copy to VGPR will be