[AArch64] Precommit test for D138904; NFC
shift + and -> shift + shift to select more shfited registers.
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chenglin.bi
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8fcf387202
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e63f64bd14
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@ -0,0 +1,297 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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; logic shift reg pattern: and
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; already optimized by another pattern
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define i64 @and_shiftedreg_from_and(i64 %a, i64 %b) {
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; CHECK-LABEL: and_shiftedreg_from_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and x8, x1, x0, asr #23
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; CHECK-NEXT: and x0, x8, #0xffffffffff000000
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; CHECK-NEXT: ret
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%ashr = ashr i64 %a, 23
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%and = and i64 %ashr, -16777216
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%r = and i64 %b, %and
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ret i64 %r
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}
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; TODO: logic shift reg pattern: bic
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define i64 @bic_shiftedreg_from_and(i64 %a, i64 %b) {
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; CHECK-LABEL: bic_shiftedreg_from_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #16777215
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; CHECK-NEXT: orn x8, x8, x0, asr #23
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; CHECK-NEXT: and x0, x1, x8
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; CHECK-NEXT: ret
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%ashr = ashr i64 %a, 23
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%and = and i64 %ashr, -16777216
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%not = xor i64 %and, -1
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%r = and i64 %b, %not
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ret i64 %r
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}
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; logic shift reg pattern: eon
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define i64 @eon_shiftedreg_from_and(i64 %a, i64 %b) {
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; CHECK-LABEL: eon_shiftedreg_from_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x8, x0, #36
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; CHECK-NEXT: and x8, x8, #0xffe0000000000000
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; CHECK-NEXT: eon x0, x8, x1
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; CHECK-NEXT: ret
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%shl = shl i64 %a, 36
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%and = and i64 %shl, -9007199254740992
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%xor = xor i64 %and, -1
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%r = xor i64 %b, %xor
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ret i64 %r
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}
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; logic shift reg pattern: eor
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define i64 @eor_shiftedreg_from_and(i64 %a, i64 %b) {
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; CHECK-LABEL: eor_shiftedreg_from_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, #23
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; CHECK-NEXT: and x8, x8, #0x1ffff000000
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; CHECK-NEXT: eor x0, x8, x1
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; CHECK-NEXT: ret
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%lshr = lshr i64 %a, 23
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%and = and i64 %lshr, 2199006478336
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%or = xor i64 %and, %b
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ret i64 %or
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}
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; logic shift reg pattern: mvn
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; already optimized by another pattern
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define i64 @mvn_shiftedreg_from_and(i64 %a) {
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; CHECK-LABEL: mvn_shiftedreg_from_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #9007199254740991
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; CHECK-NEXT: orn x0, x8, x0, lsl #36
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; CHECK-NEXT: ret
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%shl = shl i64 %a, 36
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%and = and i64 %shl, -9007199254740992
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%xor = xor i64 %and, -1
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ret i64 %xor
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}
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; logic shift reg pattern: orn
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; already optimized by another pattern
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define i64 @orn_shiftedreg_from_and(i64 %a, i64 %b) {
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; CHECK-LABEL: orn_shiftedreg_from_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orn x8, x1, x0, lsr #23
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; CHECK-NEXT: orr x0, x8, #0xfffffe0000ffffff
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; CHECK-NEXT: ret
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%lshr = lshr i64 %a, 23
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%and = and i64 %lshr, 2199006478336
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%not = xor i64 %and, -1
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%or = or i64 %not, %b
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ret i64 %or
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}
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; logic shift reg pattern: orr
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; srl constant bitwidth == (lowbits + masklen + shiftamt)
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define i64 @orr_shiftedreg_from_and(i64 %a, i64 %b) {
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; CHECK-LABEL: orr_shiftedreg_from_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, #23
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; CHECK-NEXT: and x8, x8, #0x1ffff000000
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; CHECK-NEXT: orr x0, x8, x1
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; CHECK-NEXT: ret
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%lshr = lshr i64 %a, 23
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%and = and i64 %lshr, 2199006478336 ; 0x1ffff000000
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%or = or i64 %and, %b
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ret i64 %or
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}
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; logic shift reg pattern: orr
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; srl constant bitwidth < (lowbits + masklen + shiftamt)
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define i64 @orr_shiftedreg_from_and_mask2(i64 %a, i64 %b) {
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; CHECK-LABEL: orr_shiftedreg_from_and_mask2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, #23
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; CHECK-NEXT: and x8, x8, #0x1ffff000000
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; CHECK-NEXT: orr x0, x8, x1
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; CHECK-NEXT: ret
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%lshr = lshr i64 %a, 23
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%and = and i64 %lshr, 4398029733888 ; 0x3ffff000000
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%or = or i64 %and, %b
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ret i64 %or
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}
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; arithmetic shift reg pattern: add
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define i32 @add_shiftedreg_from_and(i32 %a, i32 %b) {
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; CHECK-LABEL: add_shiftedreg_from_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #3
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; CHECK-NEXT: and w8, w8, #0xff000000
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; CHECK-NEXT: add w0, w8, w1
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; CHECK-NEXT: ret
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%ashr = ashr i32 %a, 3
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%and = and i32 %ashr, -16777216
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%add = add i32 %and, %b
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ret i32 %add
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}
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; arithmetic shift reg pattern: sub
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define i64 @sub_shiftedreg_from_and_shl(i64 %a, i64 %b) {
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; CHECK-LABEL: sub_shiftedreg_from_and_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x8, x0, #36
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; CHECK-NEXT: and x8, x8, #0xffe0000000000000
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; CHECK-NEXT: sub x0, x1, x8
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; CHECK-NEXT: ret
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%shl = shl i64 %a, 36
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%and = and i64 %shl, -9007199254740992
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%sub = sub i64 %b, %and
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ret i64 %sub
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}
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; negative test: type is not i32 or i64
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define <2 x i32> @shiftedreg_from_and_negative_type(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_type:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.2s, v0.2s, #2
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; CHECK-NEXT: bic v0.2s, #31
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; CHECK-NEXT: sub v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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%shl = shl <2 x i32> %a, <i32 2, i32 2>
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%and = and <2 x i32> %shl, <i32 -32, i32 -32>
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%sub = sub <2 x i32> %b, %and
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ret <2 x i32> %sub
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}
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; negative test: shift one-use
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define i32 @shiftedreg_from_and_negative_oneuse1(i32 %a, i32 %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_oneuse1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #23
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; CHECK-NEXT: and w9, w8, #0xff000000
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; CHECK-NEXT: add w9, w9, w1
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; CHECK-NEXT: mul w0, w8, w9
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; CHECK-NEXT: ret
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%ashr = ashr i32 %a, 23
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%and = and i32 %ashr, -16777216
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%add = add i32 %and, %b
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%r = mul i32 %ashr, %add
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ret i32 %r
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}
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; negative test: and one-use
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define i32 @shiftedreg_from_and_negative_oneuse2(i32 %a, i32 %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_oneuse2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #23
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; CHECK-NEXT: and w8, w8, #0xff000000
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; CHECK-NEXT: add w9, w8, w1
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; CHECK-NEXT: mul w0, w8, w9
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; CHECK-NEXT: ret
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%ashr = ashr i32 %a, 23
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%and = and i32 %ashr, -16777216
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%add = add i32 %and, %b
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%r = mul i32 %and, %add
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ret i32 %r
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}
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; negative test: and c is not mask
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define i32 @shiftedreg_from_and_negative_andc1(i32 %a, i32 %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_andc1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #26215
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; CHECK-NEXT: movk w8, #65510, lsl #16
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; CHECK-NEXT: and w8, w8, w0, asr #23
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; CHECK-NEXT: add w0, w8, w1
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; CHECK-NEXT: ret
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%ashr = ashr i32 %a, 23
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%and = and i32 %ashr, -1677721
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%add = add i32 %and, %b
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ret i32 %add
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}
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; negative test: sra with and c is not legal mask
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define i32 @shiftedreg_from_and_negative_andc2(i32 %a, i32 %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_andc2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-285212672
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; CHECK-NEXT: and w8, w8, w0, asr #23
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; CHECK-NEXT: add w0, w8, w1
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; CHECK-NEXT: ret
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%ashr = ashr i32 %a, 23
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%and = and i32 %ashr, 4009754624 ; 0xef000000
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%add = add i32 %and, %b
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ret i32 %add
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}
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; negative test: shl with and c is not legal mask
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define i64 @shiftedreg_from_and_negative_andc3(i64 %a, i64 %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_andc3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x0, x1, x0, lsl #36
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; CHECK-NEXT: ret
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%shl = shl i64 %a, 36
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%and = and i64 %shl, -4294967296
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%xor = xor i64 %and, %b
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ret i64 %xor
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}
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; negative test: shl with and c is not legal mask
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define i64 @shiftedreg_from_and_negative_andc4(i64 %a, i64 %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_andc4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x8, x0, #36
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; CHECK-NEXT: and x8, x8, #0x7fe0000000000000
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; CHECK-NEXT: eor x0, x8, x1
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; CHECK-NEXT: ret
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%shl = shl i64 %a, 36
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%and = and i64 %shl, 9214364837600034816
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%xor = xor i64 %and, %b
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ret i64 %xor
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}
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; negative test: sra with and c is not legal mask
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define i32 @shiftedreg_from_and_negative_andc5(i32 %a, i32 %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_andc5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #23
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; CHECK-NEXT: and w8, w8, #0xff000000
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; CHECK-NEXT: add w0, w8, w1
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; CHECK-NEXT: ret
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%ashr = ashr i32 %a, 23
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%and = and i32 %ashr, -16777216
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%add = add i32 %and, %b
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ret i32 %add
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}
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; negative test: srl with and c is not legal mask
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; srl constant bitwidth > (lowbits + masklen + shiftamt)
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define i64 @shiftedreg_from_and_negative_andc6(i64 %a, i64 %b) {
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; CHECK-LABEL: shiftedreg_from_and_negative_andc6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, #2
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; CHECK-NEXT: and x8, x8, #0x6
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; CHECK-NEXT: add x0, x8, x1
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; CHECK-NEXT: ret
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%lshr = lshr i64 %a, 2
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%and = and i64 %lshr, 6
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%add = add i64 %and, %b
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ret i64 %add
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}
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