[VENTUS][RISCV] Fix rd,rs1,rs2,rs3 register ordering in regext insertion pass.

Summary: Encoding register ordering in tablegen.

Test Plan: llvm/test/CodeGen/RISCV/VentusGPGPU/builtin-noverify.ll

Reviewers: zhoujing, hualin

Reviewed By: zhoujing

Differential Revision: http://www.tpt.com/D638

llvm/lib/Target/RISCV/RISCVInstrFormats.td

@@ -270,6 +270,8 @@ class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1,$rs2 = 2";
 }
 
 class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
@@ -287,6 +289,8 @@ class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1,$rs2 = 2,$rs3 = 3";
 }
 
 class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
@@ -305,6 +309,8 @@ class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
   let Inst{14-12} = frm;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1,$rs2 = 2,$rs3 = 3";
 }
 
 class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
@@ -323,6 +329,8 @@ class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1,$rs2 = 2";
 }
 
 class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
@@ -339,6 +347,8 @@ class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
   let Inst{14-12} = frm;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1,$rs2 = 2";
 }
 
 class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -353,6 +363,8 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1";
 }
 
 class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
@@ -369,6 +381,8 @@ class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1";
 }
 
 class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
@@ -384,6 +398,8 @@ class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1";
 }
 
 class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -399,6 +415,8 @@ class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
   let Inst{14-12} = funct3;
   let Inst{11-7} = imm12{4-0};
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rs1 = 1,$rs2 = 2";
 }
 
 class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -416,6 +434,8 @@ class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
   let Inst{11-8} = imm12{3-0};
   let Inst{7} = imm12{10};
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rs1 = 1,$rs2 = 2";
 }
 
 class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
@@ -427,6 +447,8 @@ class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
   let Inst{31-12} = imm20;
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0";
 }
 
 class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
@@ -441,6 +463,8 @@ class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
   let Inst{19-12} = imm20{18-11};
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
+
+  let CustomConstraints = "$rd = 0";
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

@@ -274,6 +274,8 @@ class RVBUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3,
     : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
               opcodestr, "$rd, $rs1"> {
   let rs2 = funct5;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1";
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in

llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td

@@ -40,6 +40,8 @@ class CBO_r<bits<12> optype, string opcodestr>
               opcodestr, "$rs1"> {
   let imm12 = optype;
   let rd = 0b00000;
+
+  let CustomConstraints = "$rs1 = 1";
 }
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
@@ -48,6 +50,8 @@ class Prefetch_ri<bits<5> optype, string opcodestr>
               opcodestr, "${imm12}(${rs1})"> {
   let Inst{11-7} = 0b00000;
   let rs2 = optype;
+
+  let CustomConstraints = "$rs1 = 1";
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/VentusInstrFormatsV.td

@@ -100,6 +100,8 @@ class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
   let IsVVALUInstr = 1;
+
+  let CustomConstraints = "$vd = 0,$vs1 = 1,$vs2 = 2";
 }
 
 // vALU branch
@@ -118,6 +120,8 @@ class RVInstVB<bits<3> funct3, dag outs, dag ins,
   let Inst{11-8} = imm12{3-0};
   let Inst{7} = imm12{10};
   let Opcode = OPC_CUSTOM_2.Value;
+
+  let CustomConstraints = "$vs1 = 1,$vs2 = 2";
 }
 
 class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
@@ -134,6 +138,8 @@ class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
+
+  let CustomConstraints = "$vd = 0,$rs1 = 1,$vs2 = 2";
 }
 
 class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
@@ -149,6 +155,8 @@ class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
+
+  let CustomConstraints = "$vd = 0,$rs1 = 1";
 }
 
 class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
@@ -165,6 +173,8 @@ class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
   let Inst{14-12} = OPIVI.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
+
+  let CustomConstraints = "$vd = 0,$vs2 = 2";
 }
 
 class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
@@ -180,6 +190,8 @@ class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
+
+  let CustomConstraints = "$vd = 0,$vs2 = 2";
 }
 
 class RVInstVLX<bits<3> nf, bit mew, bits<3> width,
@@ -198,6 +210,8 @@ class RVInstVLX<bits<3> nf, bit mew, bits<3> width,
   let Inst{14-12} = width;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
+
+  let CustomConstraints = "$vd = 0,$rs1 = 1,$vs2 = 2";
 }
 
 class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
@@ -216,6 +230,8 @@ class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
   let Inst{14-12} = width;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
+
+  let CustomConstraints = "$vd = 0,$rs1 = 1";
 }
 
 class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
@@ -234,6 +250,8 @@ class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
   let Inst{14-12} = width;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
+
+  let CustomConstraints = "$vs3 = 0,$rs1 = 1";
 }
 
 class RVInstVSX<bits<3> nf, bit mew, bits<3> width,
@@ -252,4 +270,6 @@ class RVInstVSX<bits<3> nf, bit mew, bits<3> width,
   let Inst{14-12} = width;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
+
+  let CustomConstraints = "$vs3 = 0,$rs1 = 1,$vs2 = 2";
 }

llvm/lib/Target/RISCV/VentusInstrInfo.td

@@ -708,6 +708,8 @@ class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
     : RVInstR<funct7, 0b100, OPC_SYSTEM, (outs GPR:$rd),
               (ins GPRMemZeroOffset:$rs1), opcodestr, "$rd, $rs1"> {
   let rs2 = funct5;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1";
 }
 }
 
@@ -725,6 +727,8 @@ class HStore_rr<bits<7> funct7, string opcodestr>
               (ins GPR:$rs2, GPRMemZeroOffset:$rs1),
                opcodestr, "$rs2, $rs1"> {
   let rd = 0;
+
+  let CustomConstraints = "$rs1 = 1,$rs2 = 2";
 }
 }
 
@@ -777,12 +781,14 @@ class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
   let isCommutable = Commutable;
 }
 
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+    CustomConstraints = "$rs1 = 1,$rs2 = 2" in
 class Priv<string opcodestr, bits<7> funct7>
     : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
               opcodestr, "">;
 
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+    CustomConstraints = "$rs1 = 1,$rs2 = 2" in
 class Priv_rr<string opcodestr, bits<7> funct7>
     : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
               opcodestr, "$rs1, $rs2"> {
@@ -870,7 +876,7 @@ def AND  : ALU_rr<0b0000000, 0b111, "and", /*Commutable*/1>,
            Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 
 
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0, CustomConstraints = "" in {
 def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
                     (ins fencearg:$pred, fencearg:$succ),
                     "fence", "$pred, $succ">, Sched<[]> {
@@ -994,6 +1000,8 @@ def ENDPRG : RVInstI<0b100, OPC_CUSTOM_0, (outs), (ins),
   let rd = 0;
   let Inst{31-25} = 0;
   let Inst{24-20} = rs2;
+
+  let CustomConstraints = "";
 }
 
 
@@ -1012,6 +1020,8 @@ class BarrierBase<bits<7> func7, string opcodestr> :
   let Inst{24-20} = rs2;
   let Inst{19-18} = uimm5{4-3};
   let Inst{17-15} = uimm5{2-0};
+
+  let CustomConstraints = "";
 }
 
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {

llvm/lib/Target/RISCV/VentusInstrInfoA.td

@@ -21,6 +21,8 @@ class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
                     (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
                     opcodestr, "$rd, $rs1"> {
   let rs2 = 0;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1";
 }
 
 multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {

llvm/lib/Target/RISCV/VentusInstrInfoF.td

@@ -260,6 +260,8 @@ class FPUnaryOp_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
               opcodestr, "$rd, $rs1"> {
   let rs2 = rs2val;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1";
 }
 multiclass FPUnaryOp_r_m<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
                          list<ExtInfo_rr> Exts, string opcodestr> {
@@ -277,6 +279,8 @@ class FPUnaryOp_r_frm<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
                  (ins rs1ty:$rs1, frmarg:$frm), opcodestr,
                   "$rd, $rs1, $frm"> {
   let rs2 = rs2val;
+
+  let CustomConstraints = "$rd = 0,$rs1 = 1";
 }
 multiclass FPUnaryOp_r_frm_m<bits<7> funct7, bits<5> rs2val,
                              list<ExtInfo_rr> Exts, string opcodestr> {

llvm/lib/Target/RISCV/VentusInstrInfoV.td

@@ -698,23 +698,13 @@ class VENTUS_VS<bits<3> funct3, string opcodestr>:
 
 // Local/Global memory load/store instructions
 class VENTUS_VLI12<bits<3> funct3, string opcodestr> :
-              RVInstI<funct3, OPC_CUSTOM_3, (outs VGPR:$vd),
+              RVInstI<funct3, OPC_CUSTOM_3, (outs VGPR:$rd),
-              (ins VGPRMem:$vs1, simm12:$imm12),
+              (ins VGPRMem:$rs1, simm12:$imm12),
-              opcodestr # ".v" , "$vd, ${imm12}(${vs1})">, Sched<[]> {
+              opcodestr # ".v" , "$rd, ${imm12}(${rs1})">, Sched<[]>;
-      bits<5> vs1;
-      bits<5> vd;
-      let Inst{19-15} = vs1;
-      let Inst{11-7} = vd;
-}
 class VENTUS_VSI12<bits<3> funct3, string opcodestr> :
               RVInstS<funct3, OPC_CUSTOM_3, (outs),
-              (ins VGPR:$vs2, VGPRMem:$vs1, simm12:$imm12),
+              (ins VGPR:$rs2, VGPRMem:$rs1, simm12:$imm12),
-              opcodestr # ".v", "$vs2, ${imm12}(${vs1})">, Sched<[]> {
+              opcodestr # ".v", "$rs2, ${imm12}(${rs1})">, Sched<[]>;
-      bits<5> vs1;
-      bits<5> vs2;
-      let Inst{24-20} = vs2;
-      let Inst{19-15} = vs1;
-}
 
 //===----------------------------------------------------------------------===//
 // Instructions
@@ -741,7 +731,7 @@ def SETRPC : RVInstI<0b011, OPC_CUSTOM_2, (outs GPR:$rd), (ins GPR:$rs1, simm12:
              Sched<[WriteIALU, ReadIALU]>;
 
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0, vs1 = 0, vs2 = 0,
-    imm12 = 0 in
+    imm12 = 0, CustomConstraints = "" in
 def JOIN : RVInstVB<0b010, (outs), (ins), "join", "">,
            Sched<[]>;
 
@@ -1097,7 +1087,7 @@ defm VFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b010011, 0b10000>;
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // Vector Floating-Point Move Instruction
 let RVVConstraint = NoConstraint in
-let vs2 = 0 in
+let vs2 = 0, CustomConstraints = "$vd = 0,$rs1 = 1" in
 def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VGPR:$vd),
                        (ins GPRF32:$rs1), "vfmv.v.f", "$vd, $rs1">,
                Sched<[WriteVFMovV_UpperBound, ReadVFMovF_UpperBound]>;
@@ -1153,7 +1143,7 @@ defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 
-let vs2 = 0 in
+let vs2 = 0, CustomConstraints = "$vd = 0" in
 def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VGPR:$vd),
                     (ins), "vid.v", "$vd">,
             Sched<[WriteVMIdxV]>;
@@ -1163,9 +1153,9 @@ let RVVConstraint = NoConstraint in {
 def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
                       (ins VGPR:$vs2), "vmv.x.s", "$vd, $vs2">,
               Sched<[WriteVIMovVX, ReadVIMovVX]>;
-let Constraints = "$vd = $vd_wb" in
+let Constraints = "$vd = $vd_rb" in
-def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VGPR:$vd_wb),
+def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VGPR:$vd),
-                      (ins VGPR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">,
+                      (ins VGPR:$vd_rb, GPR:$rs1), "vmv.s.x", "$vd, $rs1">,
               Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>;
 } // RVVConstraint = NoConstraint
 

llvm/lib/Target/RISCV/VentusRegextInsertion.cpp

@@ -26,9 +26,10 @@ namespace {
 class VentusRegextInsertion : public MachineFunctionPass {
 public:
   const RISCVInstrInfo *TII;
+  const RISCVRegisterInfo *TRI;
   static char ID;
 
-  VentusRegextInsertion() : MachineFunctionPass(ID)   {
+  VentusRegextInsertion() : MachineFunctionPass(ID) {
     initializeVentusRegextInsertionPass(*PassRegistry::getPassRegistry());
   }
 
@@ -49,6 +50,8 @@ char VentusRegextInsertion::ID = 0;
 
 bool VentusRegextInsertion::runOnMachineFunction(MachineFunction &MF) {
   TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
+  TRI = static_cast<const RISCVRegisterInfo *>(
+      MF.getSubtarget().getRegisterInfo());
   bool Modified = false;
 
   // FIXME: As this expansion pass will break def-use chain, it can not pass
@@ -63,7 +66,7 @@ bool VentusRegextInsertion::runOnMachineFunction(MachineFunction &MF) {
 
 bool VentusRegextInsertion::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
   bool Modified = false;
-  for(auto &MI : MBB) {
+  for (auto &MI : MBB) {
     Modified |= insertRegext(MBB, MI);
   }
   return Modified;
@@ -78,37 +81,29 @@ bool VentusRegextInsertion::insertRegext(MachineBasicBlock &MBB,
   unsigned Offsets = 0;
 
   for (unsigned i = 0; i < MI.getNumOperands(); ++i) {
-    unsigned RegIdx = 0;
     MachineOperand &Op = MI.getOperand(i);
-    if (!Op.isReg())
+    if (!Op.isReg() ||
+        MI.getDesc().getOperandConstraint(i, MCOI::TIED_TO) != -1)
       continue;
 
-    unsigned RegId = Op.getReg().id();
+    uint16_t RegEncodingValue = TRI->getEncodingValue(Op.getReg());
-    // FIXME: The ordering of rd, rs1, rs2, rs3 may not be the same as
+    if (RegEncodingValue > 31) {
-    // operand index 0, 1, 2, 3!
-    // TODO: Simplify this!
-    if (RISCV::GPRRegClass.contains(Op.getReg()) && RegId > RISCV::X31) {
-      // Encode overflowed GPR register numbering
-      Offsets |= (RegId - RISCV::X31 + 31) / 32 << (RegIdx * 3);
-      unsigned NewReg = RISCV::X0 + ((RegId - RISCV::X31) % 32);
-      Op.setRegIgnoreDUChain(Register(NewReg));
-      hasOverflow = true;
-    } else if (RISCV::VGPRRegClass.contains(Op.getReg()) &&
-               RegId > RISCV::V31) {
-      Offsets |= (RegId - RISCV::V31 + 31) / 32 << (RegIdx * 3);
-      unsigned NewReg = RISCV::V0 + ((RegId - RISCV::V31) % 32);
-      Op.setRegIgnoreDUChain(Register(NewReg));
       hasOverflow = true;
+      // FIXME: Support assembler/disassembler
+      int Pos = MI.getDesc().getOperandConstraint(i, MCOI::CUSTOM);
+      assert(Pos != -1 && "Out of range[0, 31] register operand custom "
+                          "constraint that must be present.");
+      Offsets |= (RegEncodingValue >> 5 & 0x7) << (3 * Pos);
     }
-
-    RegIdx++;
   }
 
   if (hasOverflow) {
     DebugLoc DL = MI.getDebugLoc();
     // Create instruction to expand register basic offset as imm * 32
     BuildMI(MBB, &MI, DL, TII->get(RISCV::REGEXT))
-      .addReg(RISCV::X0).addReg(RISCV::X0).addImm(Offsets);
+        .addReg(RISCV::X0)
+        .addReg(RISCV::X0)
+        .addImm(Offsets);
   }
 
   return hasOverflow;

llvm/test/CodeGen/RISCV/VentusGPGPU/builtin-noverify.ll

@@ -10,23 +10,23 @@ define dso_local void @foo_fun(ptr addrspace(1) nocapture noundef %A, ptr addrsp
 ; VENTUS-NEXT:    addi tp, tp, 8
 ; VENTUS-NEXT:    .cfi_def_cfa_offset 8
 ; VENTUS-NEXT:    regext zero, zero, 1
-; VENTUS-NEXT:    vmv.v.x v1, tp
+; VENTUS-NEXT:    vmv.v.x v32, tp
 ; VENTUS-NEXT:    sw ra, -4(sp) # 4-byte Folded Spill
 ; VENTUS-NEXT:    .cfi_offset ra, 8
 ; VENTUS-NEXT:    .cfi_offset v33.l, 4
 ; VENTUS-NEXT:    .cfi_offset v34.l, 0
 ; VENTUS-NEXT:    regext zero, zero, 1
-; VENTUS-NEXT:    vadd.vx v2, v1, zero
+; VENTUS-NEXT:    vadd.vx v33, v1, zero
 ; VENTUS-NEXT:    regext zero, zero, 1
-; VENTUS-NEXT:    vadd.vx v3, v0, zero
+; VENTUS-NEXT:    vadd.vx v34, v0, zero
 ; VENTUS-NEXT:    vmv.v.x v0, zero
 ; VENTUS-NEXT:    call _Z13get_global_idj
 ; VENTUS-NEXT:    vsll.vi v0, v0, 2
-; VENTUS-NEXT:    regext zero, zero, 1
+; VENTUS-NEXT:    regext zero, zero, 64
-; VENTUS-NEXT:    vadd.vv v1, v2, v0
+; VENTUS-NEXT:    vadd.vv v1, v33, v0
 ; VENTUS-NEXT:    vlw12.v v1, 0(v1)
-; VENTUS-NEXT:    regext zero, zero, 1
+; VENTUS-NEXT:    regext zero, zero, 64
-; VENTUS-NEXT:    vadd.vv v0, v3, v0
+; VENTUS-NEXT:    vadd.vv v0, v34, v0
 ; VENTUS-NEXT:    vlw12.v v2, 0(v0)
 ; VENTUS-NEXT:    vadd.vv v1, v2, v1
 ; VENTUS-NEXT:    vsw12.v v1, 0(v0)