[AArch64][SME]: Add streaming-compatible testing files.
Testing files: - subvector.ll - permute-rev.ll - permute-zip-uzp-trn.ll - vector-shuffle.ll Reviewed By: david-arm, sdesmalen Differential Revision: https://reviews.llvm.org/D138683
This commit is contained in:
Hassnaa Hamdi
parent
a3b745818d
commit
de7222b2dd
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@ -0,0 +1,240 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; REVB pattern for shuffle v32i8 -> v16i16
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define void @test_revbv16i16(ptr %a) #0 {
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; CHECK-LABEL: test_revbv16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: revb z0.h, p0/m, z0.h
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; CHECK-NEXT: revb z1.h, p0/m, z1.h
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <32 x i8>, ptr %a
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%tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14, i32 17, i32 16, i32 19, i32 18, i32 21, i32 20, i32 23, i32 22, i32 undef, i32 24, i32 27, i32 undef, i32 29, i32 28, i32 undef, i32 undef>
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store <32 x i8> %tmp2, ptr %a
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ret void
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}
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; REVB pattern for shuffle v32i8 -> v8i32
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define void @test_revbv8i32(ptr %a) #0 {
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; CHECK-LABEL: test_revbv8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: revb z0.s, p0/m, z0.s
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; CHECK-NEXT: revb z1.s, p0/m, z1.s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <32 x i8>, ptr %a
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%tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12, i32 19, i32 18, i32 17, i32 16, i32 23, i32 22, i32 21, i32 20, i32 27, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 29, i32 undef>
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store <32 x i8> %tmp2, ptr %a
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ret void
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}
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; REVB pattern for shuffle v32i8 -> v4i64
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define void @test_revbv4i64(ptr %a) #0 {
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; CHECK-LABEL: test_revbv4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: revb z0.d, p0/m, z0.d
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; CHECK-NEXT: revb z1.d, p0/m, z1.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <32 x i8>, ptr %a
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%tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 31, i32 30, i32 29, i32 undef, i32 27, i32 undef, i32 undef, i32 undef>
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store <32 x i8> %tmp2, ptr %a
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ret void
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}
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; REVH pattern for shuffle v16i16 -> v8i32
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define void @test_revhv8i32(ptr %a) #0 {
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; CHECK-LABEL: test_revhv8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: revh z0.s, p0/m, z0.s
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; CHECK-NEXT: revh z1.s, p0/m, z1.s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <16 x i16>, ptr %a
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%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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store <16 x i16> %tmp2, ptr %a
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ret void
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}
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; REVH pattern for shuffle v16f16 -> v8f32
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define void @test_revhv8f32(ptr %a) #0 {
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; CHECK-LABEL: test_revhv8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: revh z0.s, p0/m, z0.s
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; CHECK-NEXT: revh z1.s, p0/m, z1.s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <16 x half>, ptr %a
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%tmp2 = shufflevector <16 x half> %tmp1, <16 x half> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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store <16 x half> %tmp2, ptr %a
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ret void
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}
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; REVH pattern for shuffle v16i16 -> v4i64
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define void @test_revhv4i64(ptr %a) #0 {
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; CHECK-LABEL: test_revhv4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: revh z0.d, p0/m, z0.d
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; CHECK-NEXT: revh z1.d, p0/m, z1.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <16 x i16>, ptr %a
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%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
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store <16 x i16> %tmp2, ptr %a
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ret void
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}
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; REVW pattern for shuffle v8i32 -> v4i64
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define void @test_revwv4i64(ptr %a) #0 {
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; CHECK-LABEL: test_revwv4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: revw z0.d, p0/m, z0.d
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; CHECK-NEXT: revw z1.d, p0/m, z1.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i32>, ptr %a
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%tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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store <8 x i32> %tmp2, ptr %a
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ret void
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}
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; REVW pattern for shuffle v8f32 -> v4f64
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define void @test_revwv4f64(ptr %a) #0 {
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; CHECK-LABEL: test_revwv4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: revw z0.d, p0/m, z0.d
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; CHECK-NEXT: revw z1.d, p0/m, z1.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <8 x float>, ptr %a
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%tmp2 = shufflevector <8 x float> %tmp1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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store <8 x float> %tmp2, ptr %a
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ret void
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}
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define <16 x i8> @test_revv16i8(ptr %a) #0 {
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; CHECK-LABEL: test_revv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: revb z0.d, p0/m, z0.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%tmp1 = load <16 x i8>, ptr %a
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
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ret <16 x i8> %tmp2
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}
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; REVW pattern for shuffle two v8i32 inputs with the second input available.
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define void @test_revwv8i32v8i32(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: test_revwv8i32v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x1]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: revw z0.d, p0/m, z0.d
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; CHECK-NEXT: revw z1.d, p0/m, z1.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i32>, ptr %a
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%tmp2 = load <8 x i32>, ptr %b
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%tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> <i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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store <8 x i32> %tmp3, ptr %a
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ret void
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}
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define void @test_revhv32i16(ptr %a) #0 {
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; CHECK-LABEL: test_revhv32i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0, #32]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: revh z0.d, p0/m, z0.d
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; CHECK-NEXT: ldp q2, q3, [x0]
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; CHECK-NEXT: revh z1.d, p0/m, z1.d
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; CHECK-NEXT: stp q0, q1, [x0, #32]
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; CHECK-NEXT: revh z0.d, p0/m, z2.d
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; CHECK-NEXT: revh z1.d, p0/m, z3.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <32 x i16>, ptr %a
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%tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <32 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12, i32 19, i32 18, i32 17, i32 16, i32 23, i32 22, i32 21, i32 20, i32 27, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 29, i32 undef>
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store <32 x i16> %tmp2, ptr %a
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ret void
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}
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define void @test_rev_elts_fail(ptr %a) #0 {
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; CHECK-LABEL: test_rev_elts_fail:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: fmov x10, d1
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; CHECK-NEXT: mov z2.d, z0.d[1]
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: fmov x9, d2
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; CHECK-NEXT: mov z0.d, z1.d[1]
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; CHECK-NEXT: fmov x11, d0
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; CHECK-NEXT: stp x9, x8, [sp, #-32]!
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: stp x11, x10, [sp, #16]
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; CHECK-NEXT: ldp q1, q0, [sp]
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i64>, ptr %a
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%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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store <4 x i64> %tmp2, ptr %a
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ret void
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}
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define void @test_revv8i32(ptr %a) #0 {
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; CHECK-LABEL: test_revv8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: mov z2.s, z0.s[1]
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; CHECK-NEXT: mov z3.s, z0.s[2]
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; CHECK-NEXT: mov z4.s, z0.s[3]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: fmov w9, s2
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; CHECK-NEXT: fmov w10, s3
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; CHECK-NEXT: fmov w11, s4
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; CHECK-NEXT: mov z0.s, z1.s[1]
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; CHECK-NEXT: mov z2.s, z1.s[2]
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; CHECK-NEXT: mov z3.s, z1.s[3]
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; CHECK-NEXT: stp w9, w8, [sp, #24]
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: stp w11, w10, [sp, #16]
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; CHECK-NEXT: fmov w10, s2
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; CHECK-NEXT: fmov w11, s3
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; CHECK-NEXT: stp w9, w8, [sp, #8]
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; CHECK-NEXT: stp w11, w10, [sp]
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; CHECK-NEXT: ldp q0, q1, [sp]
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i32>, ptr %a
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%tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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store <8 x i32> %tmp2, ptr %a
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,341 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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; Test we can code generater patterns of the form:
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; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
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; scalable_vector = ISD::INSERT_SUBVECTOR scalable_vector, fixed_length_vector, 0
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;
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; NOTE: Currently shufflevector does not support scalable vectors so it cannot
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; be used to model the above operations. Instead these tests rely on knowing
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; how fixed length operation are lowered to scalable ones, with multiple blocks
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; ensuring insert/extract sequences are not folded away.
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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; i8
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define void @subvector_v4i8(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v4i8:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: uunpklo z0.h, z0.b
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; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x i8>, ptr %in
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br label %bb1
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bb1:
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store <4 x i8> %a, ptr %out
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ret void
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}
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define void @subvector_v8i8(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v8i8:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x i8>, ptr %in
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br label %bb1
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bb1:
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store <8 x i8> %a, ptr %out
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ret void
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}
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define void @subvector_v16i8(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v16i8:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x i8>, ptr %in
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br label %bb1
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bb1:
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store <16 x i8> %a, ptr %out
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ret void
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}
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define void @subvector_v32i8(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v32i8:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%a = load <32 x i8>, ptr %in
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br label %bb1
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bb1:
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store <32 x i8> %a, ptr %out
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ret void
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}
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; i16
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define void @subvector_v2i16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v2i16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldrh w8, [x0, #2]
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: str w8, [sp, #12]
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: str w8, [sp, #8]
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; CHECK-NEXT: ldr d0, [sp, #8]
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; CHECK-NEXT: st1h { z0.s }, p0, [x1]
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <2 x i16>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <2 x i16> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v4i16(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v4i16:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr d0, [x0]
|
||||
; CHECK-NEXT: str d0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <4 x i16>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <4 x i16> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v8i16(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v8i16:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr q0, [x0]
|
||||
; CHECK-NEXT: str q0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <8 x i16>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <8 x i16> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v16i16(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v16i16:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <16 x i16>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <16 x i16> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; i32
|
||||
define void @subvector_v2i32(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v2i32:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr d0, [x0]
|
||||
; CHECK-NEXT: str d0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <2 x i32>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <2 x i32> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v4i32(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v4i32:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr q0, [x0]
|
||||
; CHECK-NEXT: str q0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <4 x i32>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <4 x i32> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v8i32(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v8i32:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <8 x i32>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <8 x i32> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; i64
|
||||
define void @subvector_v2i64(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v2i64:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr q0, [x0]
|
||||
; CHECK-NEXT: str q0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <2 x i64>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <2 x i64> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v4i64(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v4i64:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <4 x i64>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <4 x i64> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; f16
|
||||
define void @subvector_v2f16(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v2f16:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr w8, [x0]
|
||||
; CHECK-NEXT: str w8, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <2 x half>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <2 x half> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v4f16(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v4f16:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr d0, [x0]
|
||||
; CHECK-NEXT: str d0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <4 x half>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <4 x half> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v8f16(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v8f16:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr q0, [x0]
|
||||
; CHECK-NEXT: str q0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <8 x half>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <8 x half> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v16f16(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v16f16:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <16 x half>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <16 x half> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; f32
|
||||
define void @subvector_v2f32(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v2f32:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr d0, [x0]
|
||||
; CHECK-NEXT: str d0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <2 x float>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <2 x float> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v4f32(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v4f32:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr q0, [x0]
|
||||
; CHECK-NEXT: str q0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <4 x float>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <4 x float> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v8f32(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v8f32:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <8 x float>,ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <8 x float> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; f64
|
||||
define void @subvector_v2f64(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v2f64:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldr q0, [x0]
|
||||
; CHECK-NEXT: str q0, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <2 x double>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <2 x double> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @subvector_v4f64(ptr %in, ptr %out) #0 {
|
||||
; CHECK-LABEL: subvector_v4f64:
|
||||
; CHECK: // %bb.0: // %bb1
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
%a = load <4 x double>, ptr %in
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
store <4 x double> %a, ptr %out
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sve" }
|
||||
|
|
@ -0,0 +1,382 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
|
||||
|
||||
target triple = "aarch64-unknown-linux-gnu"
|
||||
|
||||
define <4 x i8> @shuffle_ext_byone_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v4i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sub sp, sp, #16
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: mov z1.h, z0.h[1]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: mov z2.h, z0.h[2]
|
||||
; CHECK-NEXT: mov z0.h, z0.h[3]
|
||||
; CHECK-NEXT: fmov w9, s1
|
||||
; CHECK-NEXT: fmov w10, s2
|
||||
; CHECK-NEXT: fmov w11, s0
|
||||
; CHECK-NEXT: strh w8, [sp, #8]
|
||||
; CHECK-NEXT: strh w9, [sp, #14]
|
||||
; CHECK-NEXT: strh w10, [sp, #12]
|
||||
; CHECK-NEXT: strh w11, [sp, #10]
|
||||
; CHECK-NEXT: ldr d0, [sp, #8]
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <4 x i8> %op1, <4 x i8> %op2, <4 x i32> <i32 0, i32 3, i32 2, i32 1>
|
||||
ret <4 x i8> %ret
|
||||
}
|
||||
|
||||
define <8 x i8> @shuffle_ext_byone_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v8i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: mov z0.b, z0.b[7]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: insr z1.b, w8
|
||||
; CHECK-NEXT: fmov d0, d1
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <8 x i8> %op1, <8 x i8> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
|
||||
ret <8 x i8> %ret
|
||||
}
|
||||
|
||||
define <16 x i8> @shuffle_ext_byone_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v16i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z0.b, z0.b[15]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: insr z1.b, w8
|
||||
; CHECK-NEXT: mov z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <16 x i8> %op1, <16 x i8> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22,
|
||||
i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
|
||||
ret <16 x i8> %ret
|
||||
}
|
||||
|
||||
define void @shuffle_ext_byone_v32i8(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v32i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: ldr q1, [x1]
|
||||
; CHECK-NEXT: mov z0.b, z0.b[15]
|
||||
; CHECK-NEXT: mov z2.b, z1.b[15]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: ldr q0, [x1, #16]
|
||||
; CHECK-NEXT: fmov w9, s2
|
||||
; CHECK-NEXT: insr z1.b, w8
|
||||
; CHECK-NEXT: insr z0.b, w9
|
||||
; CHECK-NEXT: stp q1, q0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <32 x i8>, ptr %a
|
||||
%op2 = load <32 x i8>, ptr %b
|
||||
%ret = shufflevector <32 x i8> %op1, <32 x i8> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38,
|
||||
i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46,
|
||||
i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54,
|
||||
i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62>
|
||||
store <32 x i8> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x i16> @shuffle_ext_byone_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v2i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: ptrue p0.d
|
||||
; CHECK-NEXT: revw z0.d, p0/m, z0.d
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <2 x i16> %op1, <2 x i16> %op2, <2 x i32> <i32 1, i32 0>
|
||||
ret <2 x i16> %ret
|
||||
}
|
||||
|
||||
define <4 x i16> @shuffle_ext_byone_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v4i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: mov z0.h, z0.h[3]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: insr z1.h, w8
|
||||
; CHECK-NEXT: fmov d0, d1
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <4 x i16> %op1, <4 x i16> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
|
||||
ret <4 x i16> %ret
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_ext_byone_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v8i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z0.h, z0.h[7]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: insr z1.h, w8
|
||||
; CHECK-NEXT: mov z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <8 x i16> %op1, <8 x i16> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
|
||||
ret <8 x i16> %ret
|
||||
}
|
||||
|
||||
define void @shuffle_ext_byone_v16i16(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v16i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: ldr q1, [x1]
|
||||
; CHECK-NEXT: mov z0.h, z0.h[7]
|
||||
; CHECK-NEXT: mov z2.h, z1.h[7]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: ldr q0, [x1, #16]
|
||||
; CHECK-NEXT: fmov w9, s2
|
||||
; CHECK-NEXT: insr z1.h, w8
|
||||
; CHECK-NEXT: insr z0.h, w9
|
||||
; CHECK-NEXT: stp q1, q0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <16 x i16>, ptr %a
|
||||
%op2 = load <16 x i16>, ptr %b
|
||||
%ret = shufflevector <16 x i16> %op1, <16 x i16> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22,
|
||||
i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
|
||||
store <16 x i16> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x i32> @shuffle_ext_byone_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v2i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: mov z0.s, z0.s[1]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: insr z1.s, w8
|
||||
; CHECK-NEXT: fmov d0, d1
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <2 x i32> %op1, <2 x i32> %op2, <2 x i32> <i32 1, i32 2>
|
||||
ret <2 x i32> %ret
|
||||
}
|
||||
|
||||
define <4 x i32> @shuffle_ext_byone_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z0.s, z0.s[3]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: insr z1.s, w8
|
||||
; CHECK-NEXT: mov z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <4 x i32> %op1, <4 x i32> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
|
||||
ret <4 x i32> %ret
|
||||
}
|
||||
|
||||
define void @shuffle_ext_byone_v8i32(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v8i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: ldr q1, [x1]
|
||||
; CHECK-NEXT: mov z0.s, z0.s[3]
|
||||
; CHECK-NEXT: mov z2.s, z1.s[3]
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: ldr q0, [x1, #16]
|
||||
; CHECK-NEXT: fmov w9, s2
|
||||
; CHECK-NEXT: insr z1.s, w8
|
||||
; CHECK-NEXT: insr z0.s, w9
|
||||
; CHECK-NEXT: stp q1, q0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x i32>, ptr %a
|
||||
%op2 = load <8 x i32>, ptr %b
|
||||
%ret = shufflevector <8 x i32> %op1, <8 x i32> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
|
||||
store <8 x i32> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x i64> @shuffle_ext_byone_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v2i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z0.d, z0.d[1]
|
||||
; CHECK-NEXT: fmov x8, d0
|
||||
; CHECK-NEXT: insr z1.d, x8
|
||||
; CHECK-NEXT: mov z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <2 x i64> %op1, <2 x i64> %op2, <2 x i32> <i32 1, i32 2>
|
||||
ret <2 x i64> %ret
|
||||
}
|
||||
|
||||
define void @shuffle_ext_byone_v4i64(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v4i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: ldr q1, [x1]
|
||||
; CHECK-NEXT: mov z0.d, z0.d[1]
|
||||
; CHECK-NEXT: mov z2.d, z1.d[1]
|
||||
; CHECK-NEXT: fmov x8, d0
|
||||
; CHECK-NEXT: ldr q0, [x1, #16]
|
||||
; CHECK-NEXT: fmov x9, d2
|
||||
; CHECK-NEXT: insr z1.d, x8
|
||||
; CHECK-NEXT: insr z0.d, x9
|
||||
; CHECK-NEXT: stp q1, q0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x i64>, ptr %a
|
||||
%op2 = load <4 x i64>, ptr %b
|
||||
%ret = shufflevector <4 x i64> %op1, <4 x i64> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
|
||||
store <4 x i64> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define <4 x half> @shuffle_ext_byone_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: mov z0.h, z0.h[3]
|
||||
; CHECK-NEXT: insr z1.h, h0
|
||||
; CHECK-NEXT: fmov d0, d1
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <4 x half> %op1, <4 x half> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
|
||||
ret <4 x half> %ret
|
||||
}
|
||||
|
||||
define <8 x half> @shuffle_ext_byone_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z0.h, z0.h[7]
|
||||
; CHECK-NEXT: insr z1.h, h0
|
||||
; CHECK-NEXT: mov z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <8 x half> %op1, <8 x half> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
|
||||
ret <8 x half> %ret
|
||||
}
|
||||
|
||||
define void @shuffle_ext_byone_v16f16(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v16f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q1, q2, [x1]
|
||||
; CHECK-NEXT: mov z3.h, z1.h[7]
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: insr z2.h, h3
|
||||
; CHECK-NEXT: mov z0.h, z0.h[7]
|
||||
; CHECK-NEXT: insr z1.h, h0
|
||||
; CHECK-NEXT: stp q1, q2, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <16 x half>, ptr %a
|
||||
%op2 = load <16 x half>, ptr %b
|
||||
%ret = shufflevector <16 x half> %op1, <16 x half> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22,
|
||||
i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
|
||||
store <16 x half> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x float> @shuffle_ext_byone_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: mov z0.s, z0.s[1]
|
||||
; CHECK-NEXT: insr z1.s, s0
|
||||
; CHECK-NEXT: fmov d0, d1
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <2 x float> %op1, <2 x float> %op2, <2 x i32> <i32 1, i32 2>
|
||||
ret <2 x float> %ret
|
||||
}
|
||||
|
||||
define <4 x float> @shuffle_ext_byone_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z0.s, z0.s[3]
|
||||
; CHECK-NEXT: insr z1.s, s0
|
||||
; CHECK-NEXT: mov z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <4 x float> %op1, <4 x float> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
|
||||
ret <4 x float> %ret
|
||||
}
|
||||
|
||||
define void @shuffle_ext_byone_v8f32(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v8f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q1, q2, [x1]
|
||||
; CHECK-NEXT: mov z3.s, z1.s[3]
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: insr z2.s, s3
|
||||
; CHECK-NEXT: mov z0.s, z0.s[3]
|
||||
; CHECK-NEXT: insr z1.s, s0
|
||||
; CHECK-NEXT: stp q1, q2, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x float>, ptr %a
|
||||
%op2 = load <8 x float>, ptr %b
|
||||
%ret = shufflevector <8 x float> %op1, <8 x float> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
|
||||
store <8 x float> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x double> @shuffle_ext_byone_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z0.d, z0.d[1]
|
||||
; CHECK-NEXT: insr z1.d, d0
|
||||
; CHECK-NEXT: mov z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%ret = shufflevector <2 x double> %op1, <2 x double> %op2, <2 x i32> <i32 1, i32 2>
|
||||
ret <2 x double> %ret
|
||||
}
|
||||
|
||||
define void @shuffle_ext_byone_v4f64(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_v4f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q1, q2, [x1]
|
||||
; CHECK-NEXT: mov z3.d, z1.d[1]
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: insr z2.d, d3
|
||||
; CHECK-NEXT: mov z0.d, z0.d[1]
|
||||
; CHECK-NEXT: insr z1.d, d0
|
||||
; CHECK-NEXT: stp q1, q2, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x double>, ptr %a
|
||||
%op2 = load <4 x double>, ptr %b
|
||||
%ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
|
||||
store <4 x double> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @shuffle_ext_byone_reverse(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_byone_reverse:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q1, q2, [x0]
|
||||
; CHECK-NEXT: mov z3.d, z1.d[1]
|
||||
; CHECK-NEXT: ldr q0, [x1, #16]
|
||||
; CHECK-NEXT: insr z2.d, d3
|
||||
; CHECK-NEXT: mov z0.d, z0.d[1]
|
||||
; CHECK-NEXT: insr z1.d, d0
|
||||
; CHECK-NEXT: stp q1, q2, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x double>, ptr %a
|
||||
%op2 = load <4 x double>, ptr %b
|
||||
%ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
|
||||
store <4 x double> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @shuffle_ext_invalid(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: shuffle_ext_invalid:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: ldr q1, [x1]
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x double>, ptr %a
|
||||
%op2 = load <4 x double>, ptr %b
|
||||
%ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
|
||||
store <4 x double> %ret, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sve" }
|
||||
Loading…
Reference in New Issue