From cc45687e1cb30e4f5464bfbbd43aa654128ff761 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Tue, 13 Sep 2022 15:06:11 -0700 Subject: [PATCH] [RISCV] Simpify operand index calculation in createMIROperandComment [nfc] --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 1c47ac18b1b2..cf9925135bfe 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1504,18 +1504,11 @@ std::string RISCVInstrInfo::createMIROperandComment( OpIdx == 2) { unsigned Imm = MI.getOperand(OpIdx).getImm(); RISCVVType::printVType(Imm, OS); - } else if (RISCVII::hasSEWOp(TSFlags)) { - unsigned NumOperands = MI.getNumExplicitOperands(); - bool HasPolicy = RISCVII::hasVecPolicyOp(TSFlags); - - // The SEW operand is before any policy operand. - if (OpIdx != NumOperands - HasPolicy - 1) - return std::string(); - + } else if (RISCVII::hasSEWOp(TSFlags) && + OpIdx == RISCVII::getSEWOpNum(MI.getDesc())) { unsigned Log2SEW = MI.getOperand(OpIdx).getImm(); unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); - OS << "e" << SEW; }