OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 2
Code Issues Packages Projects Releases Wiki Activity

[llvm] Use range-based for loops (NFC)

This commit is contained in:
Kazu Hirata 2021-11-28 10:04:54 -08:00
parent 8874ada906
commit c73fc74ce0
11 changed files with 28 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/CodeGen/InlineSpiller.cpp
View File

@ -581,11 +581,9 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
if (!ParentVNI) {
LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
for (MachineOperand &MO : MI.operands())
if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg())
MO.setIsUndef();
}
LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
return true;
}

3
llvm/lib/CodeGen/MachinePipeliner.cpp
View File

@ -2546,8 +2546,7 @@ void SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
unsigned Pos = 0;
for (std::deque<SUnit *>::iterator I = Insts.begin(), E = Insts.end(); I != E;
++I, ++Pos) {
for (unsigned i = 0, e = MI->getNumOperands(); i < e; ++i) {
MachineOperand &MO = MI->getOperand(i);
for (MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
continue;

3
llvm/lib/CodeGen/ModuloSchedule.cpp
View File

@ -1005,8 +1005,7 @@ void ModuloScheduleExpander::updateInstruction(MachineInstr *NewMI,
unsigned CurStageNum,
unsigned InstrStageNum,
ValueMapTy *VRMap) {
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
for (MachineOperand &MO : NewMI->operands()) {
if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
continue;
Register reg = MO.getReg();

9
llvm/lib/CodeGen/RegAllocFast.cpp
View File

@ -1258,8 +1258,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
// Free registers occupied by defs.
// Iterate operands in reverse order, so we see the implicit super register
// defs first (we added them earlier in case of <def,read-undef>).
for (unsigned I = MI.getNumOperands(); I-- > 0;) {
MachineOperand &MO = MI.getOperand(I);
for (MachineOperand &MO : llvm::reverse(MI.operands())) {
if (!MO.isReg() || !MO.isDef())
continue;
@ -1362,8 +1361,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
// Free early clobbers.
if (HasEarlyClobber) {
for (unsigned I = MI.getNumOperands(); I-- > 0; ) {
MachineOperand &MO = MI.getOperand(I);
for (MachineOperand &MO : llvm::reverse(MI.operands())) {
if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber())
continue;
// subreg defs don't free the full register. We left the subreg number
@ -1440,8 +1438,7 @@ void RegAllocFast::handleBundle(MachineInstr &MI) {
MachineBasicBlock::instr_iterator BundledMI = MI.getIterator();
++BundledMI;
while (BundledMI->isBundledWithPred()) {
for (unsigned I = 0; I < BundledMI->getNumOperands(); ++I) {
MachineOperand &MO = BundledMI->getOperand(I);
for (MachineOperand &MO : BundledMI->operands()) {
if (!MO.isReg())
continue;

3
llvm/lib/CodeGen/StackSlotColoring.cpp
View File

@ -393,8 +393,7 @@ void StackSlotColoring::RewriteInstruction(MachineInstr &MI,
SmallVectorImpl<int> &SlotMapping,
MachineFunction &MF) {
// Update the operands.
for (unsigned i = 0, ee = MI.getNumOperands(); i != ee; ++i) {
MachineOperand &MO = MI.getOperand(i);
for (MachineOperand &MO : MI.operands()) {
if (!MO.isFI())
continue;
int OldFI = MO.getIndex();

5
llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
View File

@ -88,12 +88,9 @@ MachineInstr *AArch64CondBrTuning::convertToFlagSetting(MachineInstr &MI,
// If this is already the flag setting version of the instruction (e.g., SUBS)
// just make sure the implicit-def of NZCV isn't marked dead.
if (IsFlagSetting) {
for (unsigned I = MI.getNumExplicitOperands(), E = MI.getNumOperands();
I != E; ++I) {
MachineOperand &MO = MI.getOperand(I);
for (MachineOperand &MO : MI.implicit_operands())
if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
MO.setIsDead(false);
}
return &MI;
}
bool Is64Bit;

3
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
View File

@ -6452,8 +6452,7 @@ static void fixupPHIOpBanks(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder MIB(MI);
// Go through each operand and ensure it has the same regbank.
for (unsigned OpIdx = 1; OpIdx < MI.getNumOperands(); ++OpIdx) {
MachineOperand &MO = MI.getOperand(OpIdx);
for (MachineOperand &MO : llvm::drop_begin(MI.operands())) {
if (!MO.isReg())
continue;
Register OpReg = MO.getReg();

12
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -1219,9 +1219,9 @@ int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) {
// Point the CPUser node to the replacement
U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
if (UserMI->getOperand(j).isCPI()) {
UserMI->getOperand(j).setIndex(CPEs[i].CPI);
for (MachineOperand &MO : UserMI->operands())
if (MO.isCPI()) {
MO.setIndex(CPEs[i].CPI);
break;
}
// Adjust the refcount of the clone...
@ -1601,9 +1601,9 @@ bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
BBUtils->adjustBBOffsetsAfter(&*--NewIsland->getIterator());
// Finally, change the CPI in the instruction operand to be ID.
for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
if (UserMI->getOperand(i).isCPI()) {
UserMI->getOperand(i).setIndex(ID);
for (MachineOperand &MO : UserMI->operands())
if (MO.isCPI()) {
MO.setIndex(ID);
break;
}

9
llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
View File

@ -237,12 +237,9 @@ static bool isEvenReg(unsigned Reg) {
}
static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled) {
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
MachineOperand &Op = MI.getOperand(I);
if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
continue;
Op.setIsKill(false);
}
for (MachineOperand &Op : MI.operands())
if (Op.isReg() && Op.getReg() == RegNotKilled && Op.isKill())
Op.setIsKill(false);
}
/// Returns true if it is unsafe to move a copy instruction from \p UseReg to

18
llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -1066,9 +1066,9 @@ int MipsConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset)
// Point the CPUser node to the replacement
U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
if (UserMI->getOperand(j).isCPI()) {
UserMI->getOperand(j).setIndex(CPEs[i].CPI);
for (MachineOperand &MO : UserMI->operands())
if (MO.isCPI()) {
MO.setIndex(CPEs[i].CPI);
break;
}
// Adjust the refcount of the clone...
@ -1122,9 +1122,9 @@ int MipsConstantIslands::findLongFormInRangeCPEntry
// Point the CPUser node to the replacement
U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
if (UserMI->getOperand(j).isCPI()) {
UserMI->getOperand(j).setIndex(CPEs[i].CPI);
for (MachineOperand &MO : UserMI->operands())
if (MO.isCPI()) {
MO.setIndex(CPEs[i].CPI);
break;
}
// Adjust the refcount of the clone...
@ -1392,9 +1392,9 @@ bool MipsConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) {
adjustBBOffsetsAfter(&*--NewIsland->getIterator());
// Finally, change the CPI in the instruction operand to be ID.
for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
if (UserMI->getOperand(i).isCPI()) {
UserMI->getOperand(i).setIndex(ID);
for (MachineOperand &MO : UserMI->operands())
if (MO.isCPI()) {
MO.setIndex(ID);
break;
}

4
llvm/lib/Target/X86/X86ExpandPseudo.cpp
View File

@ -209,10 +209,8 @@ void X86ExpandPseudo::expandCALL_RVMARKER(MachineBasicBlock &MBB,
llvm_unreachable("unexpected opcode");
OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr();
unsigned OpStart = 1;
bool RAXImplicitDead = false;
for (; OpStart < MI.getNumOperands(); ++OpStart) {
MachineOperand &Op = MI.getOperand(OpStart);
for (MachineOperand &Op : llvm::drop_begin(MI.operands())) {
// RAX may be 'implicit dead', if there are no other users of the return
// value. We introduce a new use, so change it to 'implicit def'.
if (Op.isReg() && Op.isImplicit() && Op.isDead() &&