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[CodeGen] Use range-based for loops (NFC)

This commit is contained in:
Kazu Hirata 2021-12-06 08:49:10 -08:00
parent a05a0c3c2f
commit c4a8928b51
7 changed files with 49 additions and 59 deletions
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29
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -1038,16 +1038,15 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
// Collect a list of virtual registers killed by the terminators.
SmallVector<Register, 4> KilledRegs;
if (LV)
for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
I != E; ++I) {
MachineInstr *MI = &*I;
for (MachineOperand &MO : MI->operands()) {
for (MachineInstr &MI :
llvm::make_range(getFirstInstrTerminator(), instr_end())) {
for (MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse() || !MO.isKill() ||
MO.isUndef())
continue;
Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg) ||
LV->getVarInfo(Reg).removeKill(*MI)) {
LV->getVarInfo(Reg).removeKill(MI)) {
KilledRegs.push_back(Reg);
LLVM_DEBUG(dbgs() << "Removing terminator kill: " << MI);
MO.setIsKill(false);
@ -1057,11 +1056,9 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
SmallVector<Register, 4> UsedRegs;
if (LIS) {
for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
I != E; ++I) {
MachineInstr *MI = &*I;
for (const MachineOperand &MO : MI->operands()) {
for (MachineInstr &MI :
llvm::make_range(getFirstInstrTerminator(), instr_end())) {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || MO.getReg() == 0)
continue;
@ -1078,9 +1075,9 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
// SlotIndexes.
SmallVector<MachineInstr*, 4> Terminators;
if (Indexes) {
for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
I != E; ++I)
Terminators.push_back(&*I);
for (MachineInstr &MI :
llvm::make_range(getFirstInstrTerminator(), instr_end()))
Terminators.push_back(&MI);
}
// Since we replaced all uses of Succ with NMBB, that should also be treated
@ -1091,9 +1088,9 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
if (Indexes) {
SmallVector<MachineInstr*, 4> NewTerminators;
for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
I != E; ++I)
NewTerminators.push_back(&*I);
for (MachineInstr &MI :
llvm::make_range(getFirstInstrTerminator(), instr_end()))
NewTerminators.push_back(&MI);
for (MachineInstr *Terminator : Terminators) {
if (!is_contained(NewTerminators, Terminator))

14
llvm/lib/CodeGen/MachinePipeliner.cpp
View File

@ -1101,17 +1101,15 @@ unsigned SwingSchedulerDAG::calculateResMII() {
// Sort the instructions by the number of available choices for scheduling,
// least to most. Use the number of critical resources as the tie breaker.
FuncUnitSorter FUS = FuncUnitSorter(MF.getSubtarget());
for (MachineBasicBlock::iterator I = MBB->getFirstNonPHI(),
E = MBB->getFirstTerminator();
I != E; ++I)
FUS.calcCriticalResources(*I);
for (MachineInstr &MI :
llvm::make_range(MBB->getFirstNonPHI(), MBB->getFirstTerminator()))
FUS.calcCriticalResources(MI);
PriorityQueue<MachineInstr *, std::vector<MachineInstr *>, FuncUnitSorter>
FuncUnitOrder(FUS);
for (MachineBasicBlock::iterator I = MBB->getFirstNonPHI(),
E = MBB->getFirstTerminator();
I != E; ++I)
FuncUnitOrder.push(&*I);
for (MachineInstr &MI :
llvm::make_range(MBB->getFirstNonPHI(), MBB->getFirstTerminator()))
FuncUnitOrder.push(&MI);
while (!FuncUnitOrder.empty()) {
MachineInstr *MI = FuncUnitOrder.top();

8
llvm/lib/CodeGen/RegisterCoalescer.cpp
View File

@ -4067,13 +4067,13 @@ void RegisterCoalescer::joinAllIntervals() {
// Coalesce intervals in MBB priority order.
unsigned CurrDepth = std::numeric_limits<unsigned>::max();
for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
for (MBBPriorityInfo &MBB : MBBs) {
// Try coalescing the collected local copies for deeper loops.
if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
if (JoinGlobalCopies && MBB.Depth < CurrDepth) {
coalesceLocals();
CurrDepth = MBBs[i].Depth;
CurrDepth = MBB.Depth;
}
copyCoalesceInMBB(MBBs[i].MBB);
copyCoalesceInMBB(MBB.MBB);
}
lateLiveIntervalUpdate();
coalesceLocals();

17
llvm/lib/CodeGen/RemoveRedundantDebugValues.cpp
View File

@ -159,20 +159,17 @@ static bool reduceDbgValsBackwardScan(MachineBasicBlock &MBB) {
SmallVector<MachineInstr *, 8> DbgValsToBeRemoved;
SmallDenseSet<DebugVariable> VariableSet;
for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
I != E; ++I) {
MachineInstr *MI = &*I;
if (MI->isDebugValue()) {
DebugVariable Var(MI->getDebugVariable(), MI->getDebugExpression(),
MI->getDebugLoc()->getInlinedAt());
for (MachineInstr &MI : llvm::reverse(MBB)) {
if (MI.isDebugValue()) {
DebugVariable Var(MI.getDebugVariable(), MI.getDebugExpression(),
MI.getDebugLoc()->getInlinedAt());
auto R = VariableSet.insert(Var);
// If it is a DBG_VALUE describing a constant as:
// DBG_VALUE 0, ...
// we just don't consider such instructions as candidates
// for redundant removal.
if (MI->isNonListDebugValue()) {
MachineOperand &Loc = MI->getDebugOperand(0);
if (MI.isNonListDebugValue()) {
MachineOperand &Loc = MI.getDebugOperand(0);
if (!Loc.isReg()) {
// If we have already encountered this variable, just stop
// tracking it.
@ -185,7 +182,7 @@ static bool reduceDbgValsBackwardScan(MachineBasicBlock &MBB) {
// We have already encountered the value for this variable,
// so this one can be deleted.
if (!R.second)
DbgValsToBeRemoved.push_back(MI);
DbgValsToBeRemoved.push_back(&MI);
continue;
}

7
llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
View File

@ -168,10 +168,9 @@ void ResourcePriorityQueue::initNodes(std::vector<SUnit> &sunits) {
SUnits = &sunits;
NumNodesSolelyBlocking.resize(SUnits->size(), 0);
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
SUnit *SU = &(*SUnits)[i];
initNumRegDefsLeft(SU);
SU->NodeQueueId = 0;
for (SUnit &SU : *SUnits) {
initNumRegDefsLeft(&SU);
SU.NodeQueueId = 0;
}
}

25
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -442,33 +442,32 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
bool UnitLatencies = forceUnitLatencies();
// Pass 2: add the preds, succs, etc.
for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
SUnit *SU = &SUnits[su];
SDNode *MainNode = SU->getNode();
for (SUnit &SU : SUnits) {
SDNode *MainNode = SU.getNode();
if (MainNode->isMachineOpcode()) {
unsigned Opc = MainNode->getMachineOpcode();
const MCInstrDesc &MCID = TII->get(Opc);
for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
SU.isTwoAddress = true;
break;
}
}
if (MCID.isCommutable())
SU->isCommutable = true;
SU.isCommutable = true;
}
// Find all predecessors and successors of the group.
for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
for (SDNode *N = SU.getNode(); N; N = N->getGluedNode()) {
if (N->isMachineOpcode() &&
TII->get(N->getMachineOpcode()).getImplicitDefs()) {
SU->hasPhysRegClobbers = true;
SU.hasPhysRegClobbers = true;
unsigned NumUsed = InstrEmitter::CountResults(N);
while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
--NumUsed; // Skip over unused values at the end.
if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
SU->hasPhysRegDefs = true;
SU.hasPhysRegDefs = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
@ -477,7 +476,8 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
if (isPassiveNode(OpN)) continue; // Not scheduled.
SUnit *OpSU = &SUnits[OpN->getNodeId()];
assert(OpSU && "Node has no SUnit!");
if (OpSU == SU) continue; // In the same group.
if (OpSU == &SU)
continue; // In the same group.
EVT OpVT = N->getOperand(i).getValueType();
assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
@ -508,10 +508,10 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
Dep.setLatency(OpLatency);
if (!isChain && !UnitLatencies) {
computeOperandLatency(OpN, N, i, Dep);
ST.adjustSchedDependency(OpSU, DefIdx, SU, i, Dep);
ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep);
}
if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
if (!SU.addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
// Multiple register uses are combined in the same SUnit. For example,
// we could have a set of glued nodes with all their defs consumed by
// another set of glued nodes. Register pressure tracking sees this as
@ -911,8 +911,7 @@ EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
}
}
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
SUnit *SU = Sequence[i];
for (SUnit *SU : Sequence) {
if (!SU) {
// Null SUnit* is a noop.
TII->insertNoop(*Emitter.getBlock(), InsertPos);

8
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
View File

@ -169,11 +169,11 @@ void ScheduleDAGVLIW::listScheduleTopDown() {
releaseSuccessors(&EntrySU);
// All leaves to AvailableQueue.
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
for (SUnit &SU : SUnits) {
// It is available if it has no predecessors.
if (SUnits[i].Preds.empty()) {
AvailableQueue->push(&SUnits[i]);
SUnits[i].isAvailable = true;
if (SU.Preds.empty()) {
AvailableQueue->push(&SU);
SU.isAvailable = true;
}
}