[DAG] simplifySelect - add support for vselect(0, T, F) -> F fold

We still need to add handling for the non-zero T fold (which requires getBooleanContents handling)
This commit is contained in:
Simon Pilgrim 2022-11-16 13:11:04 +00:00
parent 2a6d4c5d8a
commit a92f5a08a1
2 changed files with 9 additions and 24 deletions

View File

@ -8941,12 +8941,12 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
if (auto *CondC = dyn_cast<ConstantSDNode>(Cond)) if (auto *CondC = dyn_cast<ConstantSDNode>(Cond))
return CondC->isZero() ? F : T; return CondC->isZero() ? F : T;
// TODO: This should simplify VSELECT with constant condition using something // TODO: This should simplify VSELECT with non-zero constant condition using
// like this (but check boolean contents to be complete?): // something like this (but check boolean contents to be complete?):
// if (ISD::isBuildVectorAllOnes(Cond.getNode())) if (ConstantSDNode *CondC = isConstOrConstSplat(Cond, /*AllowUndefs*/ false,
// return T; /*AllowTruncation*/ true))
// if (ISD::isBuildVectorAllZeros(Cond.getNode())) if (CondC->isZero())
// return F; return F;
// select ?, T, T --> T // select ?, T, T --> T
if (T == F) if (T == F)

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@ -266,25 +266,10 @@ define void @blendv_split(ptr %p, <8 x i32> %cond, <8 x i32> %a, <8 x i32> %x, <
} }
; Regression test for rGea8fb3b60196 ; Regression test for rGea8fb3b60196
; FIXME: Missing fold vselect(zero, T, F) -> F
define void @vselect_concat() { define void @vselect_concat() {
; AVX1-LABEL: vselect_concat: ; AVX-LABEL: vselect_concat:
; AVX1: ## %bb.0: ## %entry ; AVX: ## %bb.0: ## %entry
; AVX1-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; AVX-NEXT: retq
; AVX1-NEXT: vmovaps %ymm0, (%rax)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: vselect_concat:
; AVX2: ## %bb.0: ## %entry
; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
; AVX2-NEXT: vmovaps %ymm0, (%rax)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512-LABEL: vselect_concat:
; AVX512: ## %bb.0: ## %entry
; AVX512-NEXT: retq
entry: entry:
%0 = load <8 x i32>, ptr undef %0 = load <8 x i32>, ptr undef
%1 = shufflevector <8 x i32> zeroinitializer, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %1 = shufflevector <8 x i32> zeroinitializer, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>