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Revert "[RISCV] Add missing VL arguments to the creation of RISCVISD::VMV_V_X_VL nodes." 

This reverts commit 4c03c9f375.

Forgot to squash
This commit is contained in:
Craig Topper 2022-10-03 12:14:30 -07:00
parent 4c03c9f375
commit a55cdcae3e
3 changed files with 9 additions and 12 deletions
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2
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
View File

@ -2366,7 +2366,6 @@ bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
if (N.getOpcode() != RISCVISD::VMV_V_X_VL || !N.getOperand(0).isUndef())
return false;
assert(N.getNumOperands() == 3 && "Unexpected number of operands");
SplatVal = N.getOperand(1);
return true;
}
@ -2380,7 +2379,6 @@ static bool selectVSplatSimmHelper(SDValue N, SDValue &SplatVal,
if (N.getOpcode() != RISCVISD::VMV_V_X_VL || !N.getOperand(0).isUndef() ||
!isa<ConstantSDNode>(N.getOperand(1)))
return false;
assert(N.getNumOperands() == 3 && "Unexpected number of operands");
int64_t SplatImm =
cast<ConstantSDNode>(N.getOperand(1))->getSExtValue();

7
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -5967,7 +5967,6 @@ SDValue RISCVTargetLowering::lowerSTEP_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
MVT VT = Op.getSimpleValueType();
assert(VT.isScalableVector() && "Expected scalable vector");
MVT XLenVT = Subtarget.getXLenVT();
auto [Mask, VL] = getDefaultScalableVLOps(VT, DL, DAG, Subtarget);
SDValue StepVec = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL);
@ -5976,7 +5975,7 @@ SDValue RISCVTargetLowering::lowerSTEP_VECTOR(SDValue Op,
if (isPowerOf2_64(StepValImm)) {
SDValue StepVal =
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT),
DAG.getConstant(Log2_64(StepValImm), DL, XLenVT), VL);
DAG.getConstant(Log2_64(StepValImm), DL, XLenVT));
StepVec = DAG.getNode(ISD::SHL, DL, VT, StepVec, StepVal);
} else {
SDValue StepVal = lowerScalarSplat(
@ -6362,7 +6361,7 @@ SDValue RISCVTargetLowering::lowerABS(SDValue Op, SelectionDAG &DAG) const {
SDValue SplatZero = DAG.getNode(
RISCVISD::VMV_V_X_VL, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
DAG.getConstant(0, DL, Subtarget.getXLenVT()), VL);
DAG.getConstant(0, DL, Subtarget.getXLenVT()));
SDValue NegX = DAG.getNode(RISCVISD::SUB_VL, DL, ContainerVT, SplatZero, X,
DAG.getUNDEF(ContainerVT), Mask, VL);
SDValue Max = DAG.getNode(RISCVISD::SMAX_VL, DL, ContainerVT, X, NegX,
@ -6712,7 +6711,7 @@ SDValue RISCVTargetLowering::lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
MVT XLenVT = Subtarget.getXLenVT();
SDValue SplatZero = DAG.getConstant(0, DL, XLenVT);
SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterimIVT,
DAG.getUNDEF(InterimIVT), SplatZero, VL);
DAG.getUNDEF(InterimIVT), SplatZero);
Result = DAG.getNode(RISCVISD::SETCC_VL, DL, DstVT,
{Result, SplatZero, DAG.getCondCode(ISD::SETNE),
DAG.getUNDEF(DstVT), Mask, VL});

12
llvm/test/CodeGen/RISCV/rvv/stepvector.ll
View File

@ -67,7 +67,7 @@ define <vscale x 8 x i8> @add_stepvector_nxv8i8() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsll.vi v8, v8, 1
; CHECK-NEXT: ret
entry:
%0 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
@ -232,7 +232,7 @@ define <vscale x 16 x i16> @add_stepvector_nxv16i16() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsll.vi v8, v8, 1
; CHECK-NEXT: ret
entry:
%0 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
@ -361,7 +361,7 @@ define <vscale x 16 x i32> @add_stepvector_nxv16i32() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsll.vi v8, v8, 1
; CHECK-NEXT: ret
entry:
%0 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
@ -466,7 +466,7 @@ define <vscale x 8 x i64> @add_stepvector_nxv8i64() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsll.vi v8, v8, 1
; CHECK-NEXT: ret
entry:
%0 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
@ -584,7 +584,7 @@ define <vscale x 16 x i64> @add_stepvector_nxv16i64() {
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vid.v v8
; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vsll.vi v8, v8, 1
; RV32-NEXT: vadd.vv v16, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
@ -595,7 +595,7 @@ define <vscale x 16 x i64> @add_stepvector_nxv16i64() {
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vid.v v8
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vsll.vi v8, v8, 1
; RV64-NEXT: vadd.vx v16, v8, a0
; RV64-NEXT: ret
entry: