From a4ac40e92f718d487898bd204517c38113afd3bb Mon Sep 17 00:00:00 2001 From: Simon Tatham Date: Thu, 20 Jan 2022 13:22:34 +0000 Subject: [PATCH] [AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs. The Armv8-R.64 architecture defines numbered MPU region registers with indices 1-15, not 0-15. So there's no such register as PRBAR0_EL2 or PRLAR0_EL1 (for example). The encodings that they would occupy are used for the unnumbered PRBAR_ELn and PRLAR_ELn registers. Reviewed By: labrinea Differential Revision: https://reviews.llvm.org/D117755 --- .../Target/AArch64/AArch64SystemOperands.td | 4 +- llvm/test/MC/AArch64/armv8r-sysreg.s | 64 +++++-------------- .../MC/Disassembler/AArch64/armv8r-sysreg.txt | 32 +++++----- 3 files changed, 34 insertions(+), 66 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index f9fe804865a5..cce5813fe6e9 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -1333,7 +1333,7 @@ def : RWSysReg<"PRBAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b000>; def : RWSysReg<"PRLAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b001>; def : RWSysReg<"PRLAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b001>; -foreach n = 0-15 in { +foreach n = 1-15 in { foreach x = 1-2 in { //Direct acces to Protection Region Base Address Register for n th MPU region def : RWSysReg