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[Hexagon] Fixes -Wrange-loop-analysis warnings 

This avoids new warnings due to D68912 adds -Wrange-loop-analysis to -Wall.

Differential Revision: https://reviews.llvm.org/D71814
This commit is contained in:
Mark de Wever 2019-12-22 19:35:02 +01:00
parent 31262d6722
commit 9c11026c1b
5 changed files with 10 additions and 10 deletions
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2
llvm/lib/Target/Hexagon/BitTracker.cpp
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@ -860,7 +860,7 @@ void BT::visitNonBranch(const MachineInstr &MI) {
<< " cell: " << ME.getCell(RU, Map) << "\n"; << " cell: " << ME.getCell(RU, Map) << "\n";
} }
dbgs() << "Outputs:\n"; dbgs() << "Outputs:\n";
for (const std::pair<unsigned, RegisterCell> &P : ResMap) { for (const std::pair<const unsigned, RegisterCell> &P : ResMap) {
RegisterRef RD(P.first); RegisterRef RD(P.first);
dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: " dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: "
<< ME.getCell(RD, ResMap) << "\n"; << ME.getCell(RD, ResMap) << "\n";

4
llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
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@ -555,7 +555,7 @@ namespace {
LLVM_ATTRIBUTE_UNUSED LLVM_ATTRIBUTE_UNUSED
raw_ostream &operator<< (raw_ostream &OS, const PrintIMap &P) { raw_ostream &operator<< (raw_ostream &OS, const PrintIMap &P) {
OS << "{\n"; OS << "{\n";
for (const std::pair<HCE::ExtenderInit,HCE::IndexList> &Q : P.IMap) { for (const std::pair<const HCE::ExtenderInit, HCE::IndexList> &Q : P.IMap) {
OS << " " << PrintInit(Q.first, P.HRI) << " -> {"; OS << " " << PrintInit(Q.first, P.HRI) << " -> {";
for (unsigned I : Q.second) for (unsigned I : Q.second)
OS << ' ' << I; OS << ' ' << I;
@ -1895,7 +1895,7 @@ bool HCE::replaceExtenders(const AssignmentMap &IMap) {
LocDefList Defs; LocDefList Defs;
bool Changed = false; bool Changed = false;
for (const std::pair<ExtenderInit,IndexList> &P : IMap) { for (const std::pair<const ExtenderInit, IndexList> &P : IMap) {
const IndexList &Idxs = P.second; const IndexList &Idxs = P.second;
if (Idxs.size() < CountThreshold) if (Idxs.size() < CountThreshold)
continue; continue;

2
llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
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@ -2335,7 +2335,7 @@ bool HexagonLoopIdiomRecognize::coverLoop(Loop *L,
continue; continue;
if (!Worklist.count(&In) && In.mayHaveSideEffects()) if (!Worklist.count(&In) && In.mayHaveSideEffects())
return false; return false;
for (const auto &K : In.users()) { for (auto K : In.users()) {
Instruction *UseI = dyn_cast<Instruction>(K); Instruction *UseI = dyn_cast<Instruction>(K);
if (!UseI) if (!UseI)
continue; continue;

2
llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
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@ -309,7 +309,7 @@ bool HexagonPacketizerList::isCallDependent(const MachineInstr &MI,
// r0 = ... // r0 = ...
// J2_jumpr r0 // J2_jumpr r0
if (DepType == SDep::Data) { if (DepType == SDep::Data) {
for (const MachineOperand MO : MI.operands()) for (const MachineOperand &MO : MI.operands())
if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit()) if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
return true; return true;
} }

10
llvm/lib/Target/Hexagon/RDFLiveness.cpp
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@ -620,7 +620,7 @@ void Liveness::computePhiInfo() {
for (NodeAddr<UseNode*> UA : PUs) { for (NodeAddr<UseNode*> UA : PUs) {
std::map<NodeId,RegisterAggr> &PUM = PhiUp[UA.Id]; std::map<NodeId,RegisterAggr> &PUM = PhiUp[UA.Id];
RegisterRef UR = PRI.normalize(UA.Addr->getRegRef(DFG)); RegisterRef UR = PRI.normalize(UA.Addr->getRegRef(DFG));
for (const std::pair<NodeId,RegisterAggr> &P : PUM) { for (const std::pair<const NodeId, RegisterAggr> &P : PUM) {
bool Changed = false; bool Changed = false;
const RegisterAggr &MidDefs = P.second; const RegisterAggr &MidDefs = P.second;
@ -636,7 +636,7 @@ void Liveness::computePhiInfo() {
// if MidDefs does not cover (R,U) // if MidDefs does not cover (R,U)
// then add (R-MidDefs,U) to RealUseMap[P] // then add (R-MidDefs,U) to RealUseMap[P]
// //
for (const std::pair<RegisterId,NodeRefSet> &T : RUM) { for (const std::pair<const RegisterId, NodeRefSet> &T : RUM) {
RegisterRef R(T.first); RegisterRef R(T.first);
// The current phi (PA) could be a phi for a regmask. It could // The current phi (PA) could be a phi for a regmask. It could
// reach a whole variety of uses that are not related to the // reach a whole variety of uses that are not related to the
@ -768,7 +768,7 @@ void Liveness::computeLiveIns() {
auto PrA = DFG.addr<BlockNode*>(PUA.Addr->getPredecessor()); auto PrA = DFG.addr<BlockNode*>(PUA.Addr->getPredecessor());
RefMap &LOX = PhiLOX[PrA.Addr->getCode()]; RefMap &LOX = PhiLOX[PrA.Addr->getCode()];
for (const std::pair<RegisterId,NodeRefSet> &RS : RUs) { for (const std::pair<const RegisterId, NodeRefSet> &RS : RUs) {
// We need to visit each individual use. // We need to visit each individual use.
for (std::pair<NodeId,LaneBitmask> P : RS.second) { for (std::pair<NodeId,LaneBitmask> P : RS.second) {
// Create a register ref corresponding to the use, and find // Create a register ref corresponding to the use, and find
@ -991,7 +991,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
RefMap LiveInCopy = LiveIn; RefMap LiveInCopy = LiveIn;
LiveIn.clear(); LiveIn.clear();
for (const std::pair<RegisterId,NodeRefSet> &LE : LiveInCopy) { for (const std::pair<const RegisterId, NodeRefSet> &LE : LiveInCopy) {
RegisterRef LRef(LE.first); RegisterRef LRef(LE.first);
NodeRefSet &NewDefs = LiveIn[LRef.Reg]; // To be filled. NodeRefSet &NewDefs = LiveIn[LRef.Reg]; // To be filled.
const NodeRefSet &OldDefs = LE.second; const NodeRefSet &OldDefs = LE.second;
@ -1105,7 +1105,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
for (auto C : IIDF[B]) { for (auto C : IIDF[B]) {
RegisterAggr &LiveC = LiveMap[C]; RegisterAggr &LiveC = LiveMap[C];
for (const std::pair<RegisterId,NodeRefSet> &S : LiveIn) for (const std::pair<const RegisterId, NodeRefSet> &S : LiveIn)
for (auto R : S.second) for (auto R : S.second)
if (MDT.properlyDominates(getBlockWithRef(R.first), C)) if (MDT.properlyDominates(getBlockWithRef(R.first), C))
LiveC.insert(RegisterRef(S.first, R.second)); LiveC.insert(RegisterRef(S.first, R.second));