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[DAG] Add freeze(sign/zero_extend_vector_inreg(x)) -> sign/zero_extend_vector_inreg(freeze(x)) folding

This commit is contained in:
Simon Pilgrim 2022-10-23 12:19:36 +01:00
parent 12c62a6718
commit 913f08b74c
2 changed files with 4 additions and 4 deletions
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2
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -4638,6 +4638,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::ZERO_EXTEND:
case ISD::TRUNCATE:
case ISD::SIGN_EXTEND_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
case ISD::BITCAST:
return false;

6
llvm/test/CodeGen/X86/freeze-vector.ll
View File

@ -16,8 +16,7 @@ define <4 x i32> @freeze_insert_subvector(<8 x i32> %a0) nounwind {
define <2 x i64> @freeze_sign_extend_vector_inreg(<16 x i8> %a0) nounwind {
; CHECK-LABEL: freeze_sign_extend_vector_inreg:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovsxbd %xmm0, %xmm0
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
; CHECK-NEXT: vpmovsxbq %xmm0, %xmm0
; CHECK-NEXT: ret{{[l|q]}}
%x = sext <16 x i8> %a0 to <16 x i32>
%y = shufflevector <16 x i32> %x, <16 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@ -30,8 +29,7 @@ define <2 x i64> @freeze_sign_extend_vector_inreg(<16 x i8> %a0) nounwind {
define <2 x i64> @freeze_zero_extend_vector_inreg(<16 x i8> %a0) nounwind {
; CHECK-LABEL: freeze_zero_extend_vector_inreg:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; CHECK-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; CHECK-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: ret{{[l|q]}}
%x = zext <16 x i8> %a0 to <16 x i32>
%y = shufflevector <16 x i32> %x, <16 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>