OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 2
Code Issues Packages Projects Releases Wiki Activity

TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFC 

Differential Revision: https://reviews.llvm.org/D22925

llvm-svn: 276997
This commit is contained in:
Sjoerd Meijer 2016-07-28 16:32:22 +00:00
parent 655e0edfd7
commit 89217f8835
23 changed files with 50 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
llvm/lib/Target/AArch64/AArch64BranchRelaxation.cpp
View File

@ -177,7 +177,7 @@ void AArch64BranchRelaxation::scanFunction() {
void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) { void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
unsigned Size = 0; unsigned Size = 0;
for (const MachineInstr &MI : MBB) for (const MachineInstr &MI : MBB)
Size += TII->GetInstSizeInBytes(MI); Size += TII->getInstSizeInBytes(MI);
BlockInfo[MBB.getNumber()].Size = Size; BlockInfo[MBB.getNumber()].Size = Size;
} }
@ -195,7 +195,7 @@ unsigned AArch64BranchRelaxation::getInstrOffset(MachineInstr *MI) const {
// Sum instructions before MI in MBB. // Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?"); assert(I != MBB->end() && "Didn't find MI in its own basic block?");
Offset += TII->GetInstSizeInBytes(*I); Offset += TII->getInstSizeInBytes(*I);
} }
return Offset; return Offset;
} }
@ -420,7 +420,7 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI); MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI);
// No need for the branch to the next block. We're adding an unconditional // No need for the branch to the next block. We're adding an unconditional
// branch to the destination. // branch to the destination.
int delta = TII->GetInstSizeInBytes(MBB->back()); int delta = TII->getInstSizeInBytes(MBB->back());
BlockInfo[MBB->getNumber()].Size -= delta; BlockInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent(); MBB->back().eraseFromParent();
// BlockInfo[SplitBB].Offset is wrong temporarily, fixed below // BlockInfo[SplitBB].Offset is wrong temporarily, fixed below
@ -446,12 +446,12 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
if (MI->getOpcode() == AArch64::Bcc) if (MI->getOpcode() == AArch64::Bcc)
invertBccCondition(MIB); invertBccCondition(MIB);
MIB.addMBB(NextBB); MIB.addMBB(NextBB);
BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB); BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB);
BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
// Remove the old conditional branch. It may or may not still be in MBB. // Remove the old conditional branch. It may or may not still be in MBB.
BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); BlockInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
MI->eraseFromParent(); MI->eraseFromParent();
// Finally, keep the block offsets up to date. // Finally, keep the block offsets up to date.

4
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -38,7 +38,7 @@ AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
/// GetInstSize - Return the number of bytes of code the specified /// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes. /// instruction may be. This returns the maximum number of bytes.
unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
const MachineBasicBlock &MBB = *MI.getParent(); const MachineBasicBlock &MBB = *MI.getParent();
const MachineFunction *MF = MBB.getParent(); const MachineFunction *MF = MBB.getParent();
const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
@ -58,7 +58,7 @@ unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
return 0; return 0;
} }
llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size"); llvm_unreachable("getInstSizeInBytes()- Unable to determin insn size");
} }
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,

2
llvm/lib/Target/AArch64/AArch64InstrInfo.h
View File

@ -39,7 +39,7 @@ public:
/// always be able to get register info as well (through this method). /// always be able to get register info as well (through this method).
const AArch64RegisterInfo &getRegisterInfo() const { return RI; } const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
unsigned GetInstSizeInBytes(const MachineInstr &MI) const; unsigned getInstSizeInBytes(const MachineInstr &MI) const;
bool isAsCheapAsAMove(const MachineInstr &MI) const override; bool isAsCheapAsAMove(const MachineInstr &MI) const override;

4
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -610,7 +610,7 @@ template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
/// GetInstSize - Return the size of the specified MachineInstr. /// GetInstSize - Return the size of the specified MachineInstr.
/// ///
unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
const MachineBasicBlock &MBB = *MI.getParent(); const MachineBasicBlock &MBB = *MI.getParent();
const MachineFunction *MF = MBB.getParent(); const MachineFunction *MF = MBB.getParent();
const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
@ -669,7 +669,7 @@ unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end(); MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
while (++I != E && I->isInsideBundle()) { while (++I != E && I->isInsideBundle()) {
assert(!I->isBundle() && "No nested bundle!"); assert(!I->isBundle() && "No nested bundle!");
Size += GetInstSizeInBytes(*I); Size += getInstSizeInBytes(*I);
} }
return Size; return Size;
} }

2
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -154,7 +154,7 @@ public:
/// GetInstSize - Returns the size of the specified MachineInstr. /// GetInstSize - Returns the size of the specified MachineInstr.
/// ///
virtual unsigned GetInstSizeInBytes(const MachineInstr &MI) const; virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const;
unsigned isLoadFromStackSlot(const MachineInstr &MI, unsigned isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override; int &FrameIndex) const override;

4
llvm/lib/Target/ARM/ARMComputeBlockSize.cpp
View File

@ -42,8 +42,8 @@ void computeBlockSize(MachineFunction *MF, MachineBasicBlock *MBB,
BBI.PostAlign = 0; BBI.PostAlign = 0;
for (MachineInstr &I : *MBB) { for (MachineInstr &I : *MBB) {
BBI.Size += TII->GetInstSizeInBytes(I); BBI.Size += TII->getInstSizeInBytes(I);
// For inline asm, GetInstSizeInBytes returns a conservative estimate. // For inline asm, getInstSizeInBytes returns a conservative estimate.
// The actual size may be smaller, but still a multiple of the instr size. // The actual size may be smaller, but still a multiple of the instr size.
if (I.isInlineAsm()) if (I.isInlineAsm())
BBI.Unalign = isThumb ? 1 : 2; BBI.Unalign = isThumb ? 1 : 2;

20
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -823,7 +823,7 @@ unsigned ARMConstantIslands::getOffsetOf(MachineInstr *MI) const {
// Sum instructions before MI in MBB. // Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?"); assert(I != MBB->end() && "Didn't find MI in its own basic block?");
Offset += TII->GetInstSizeInBytes(*I); Offset += TII->getInstSizeInBytes(*I);
} }
return Offset; return Offset;
} }
@ -1331,7 +1331,7 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
// iterates at least once. // iterates at least once.
BaseInsertOffset = BaseInsertOffset =
std::max(UserBBI.postOffset() - UPad - 8, std::max(UserBBI.postOffset() - UPad - 8,
UserOffset + TII->GetInstSizeInBytes(*UserMI) + 1); UserOffset + TII->getInstSizeInBytes(*UserMI) + 1);
DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset)); DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
} }
unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad + unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
@ -1341,9 +1341,9 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
unsigned CPUIndex = CPUserIndex+1; unsigned CPUIndex = CPUserIndex+1;
unsigned NumCPUsers = CPUsers.size(); unsigned NumCPUsers = CPUsers.size();
MachineInstr *LastIT = nullptr; MachineInstr *LastIT = nullptr;
for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI); for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
Offset < BaseInsertOffset; Offset < BaseInsertOffset;
Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) { Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
assert(MI != UserMBB->end() && "Fell off end of block"); assert(MI != UserMBB->end() && "Fell off end of block");
if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) { if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) {
CPUser &U = CPUsers[CPUIndex]; CPUser &U = CPUsers[CPUIndex];
@ -1644,7 +1644,7 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
splitBlockBeforeInstr(MI); splitBlockBeforeInstr(MI);
// No need for the branch to the next block. We're adding an unconditional // No need for the branch to the next block. We're adding an unconditional
// branch to the destination. // branch to the destination.
int delta = TII->GetInstSizeInBytes(MBB->back()); int delta = TII->getInstSizeInBytes(MBB->back());
BBInfo[MBB->getNumber()].Size -= delta; BBInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent(); MBB->back().eraseFromParent();
// BBInfo[SplitBB].Offset is wrong temporarily, fixed below // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
@ -1660,18 +1660,18 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode())) BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
.addMBB(NextBB).addImm(CC).addReg(CCReg); .addMBB(NextBB).addImm(CC).addReg(CCReg);
Br.MI = &MBB->back(); Br.MI = &MBB->back();
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
if (isThumb) if (isThumb)
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB) BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
.addImm(ARMCC::AL).addReg(0); .addImm(ARMCC::AL).addReg(0);
else else
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
// Remove the old conditional branch. It may or may not still be in MBB. // Remove the old conditional branch. It may or may not still be in MBB.
BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
MI->eraseFromParent(); MI->eraseFromParent();
adjustBBOffsetsAfter(MBB); adjustBBOffsetsAfter(MBB);
return true; return true;
@ -2084,8 +2084,8 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() {
} }
} }
unsigned NewSize = TII->GetInstSizeInBytes(*NewJTMI); unsigned NewSize = TII->getInstSizeInBytes(*NewJTMI);
unsigned OrigSize = TII->GetInstSizeInBytes(*MI); unsigned OrigSize = TII->getInstSizeInBytes(*MI);
MI->eraseFromParent(); MI->eraseFromParent();
int Delta = OrigSize - NewSize + DeadSize; int Delta = OrigSize - NewSize + DeadSize;

2
llvm/lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -1359,7 +1359,7 @@ static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
unsigned FnSize = 0; unsigned FnSize = 0;
for (auto &MBB : MF) { for (auto &MBB : MF) {
for (auto &MI : MBB) for (auto &MI : MBB)
FnSize += TII.GetInstSizeInBytes(MI); FnSize += TII.getInstSizeInBytes(MI);
} }
return FnSize; return FnSize;
} }

2
llvm/lib/Target/ARM/README-Thumb.txt
View File

@ -238,7 +238,7 @@ Thumb2.
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
Rather than having tBR_JTr print a ".align 2" and constant island pass pad it, Rather than having tBR_JTr print a ".align 2" and constant island pass pad it,
add a target specific ALIGN instruction instead. That way, GetInstSizeInBytes add a target specific ALIGN instruction instead. That way, getInstSizeInBytes
won't have to over-estimate. It can also be used for loop alignment pass. won't have to over-estimate. It can also be used for loop alignment pass.
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//

2
llvm/lib/Target/AVR/AVRInstrInfo.cpp
View File

@ -439,7 +439,7 @@ bool AVRInstrInfo::ReverseBranchCondition(
return false; return false;
} }
unsigned AVRInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
switch (Opcode) { switch (Opcode) {

2
llvm/lib/Target/AVR/AVRInstrInfo.h
View File

@ -70,7 +70,7 @@ public:
const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const; const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const; AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const; AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
unsigned GetInstSizeInBytes(const MachineInstr *MI) const; unsigned getInstSizeInBytes(const MachineInstr *MI) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,

4
llvm/lib/Target/MSP430/MSP430BranchSelector.cpp
View File

@ -70,7 +70,7 @@ bool MSP430BSel::runOnMachineFunction(MachineFunction &Fn) {
for (MachineBasicBlock &MBB : Fn) { for (MachineBasicBlock &MBB : Fn) {
unsigned BlockSize = 0; unsigned BlockSize = 0;
for (MachineInstr &MI : MBB) for (MachineInstr &MI : MBB)
BlockSize += TII->GetInstSizeInBytes(MI); BlockSize += TII->getInstSizeInBytes(MI);
BlockSizes[MBB.getNumber()] = BlockSize; BlockSizes[MBB.getNumber()] = BlockSize;
FuncSize += BlockSize; FuncSize += BlockSize;
@ -107,7 +107,7 @@ bool MSP430BSel::runOnMachineFunction(MachineFunction &Fn) {
I != E; ++I) { I != E; ++I) {
if ((I->getOpcode() != MSP430::JCC || I->getOperand(0).isImm()) && if ((I->getOpcode() != MSP430::JCC || I->getOperand(0).isImm()) &&
I->getOpcode() != MSP430::JMP) { I->getOpcode() != MSP430::JMP) {
MBBStartOffset += TII->GetInstSizeInBytes(*I); MBBStartOffset += TII->getInstSizeInBytes(*I);
continue; continue;
} }

2
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -293,7 +293,7 @@ unsigned MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB,
/// GetInstSize - Return the number of bytes of code the specified /// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes. /// instruction may be. This returns the maximum number of bytes.
/// ///
unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
const MCInstrDesc &Desc = MI.getDesc(); const MCInstrDesc &Desc = MI.getDesc();
switch (Desc.TSFlags & MSP430II::SizeMask) { switch (Desc.TSFlags & MSP430II::SizeMask) {

2
llvm/lib/Target/MSP430/MSP430InstrInfo.h
View File

@ -68,7 +68,7 @@ public:
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override; const TargetRegisterInfo *TRI) const override;
unsigned GetInstSizeInBytes(const MachineInstr &MI) const; unsigned getInstSizeInBytes(const MachineInstr &MI) const;
// Branch folding goodness // Branch folding goodness
bool bool

16
llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -801,7 +801,7 @@ void MipsConstantIslands::computeBlockSize(MachineBasicBlock *MBB) {
BBI.Size = 0; BBI.Size = 0;
for (const MachineInstr &MI : *MBB) for (const MachineInstr &MI : *MBB)
BBI.Size += TII->GetInstSizeInBytes(MI); BBI.Size += TII->getInstSizeInBytes(MI);
} }
/// getOffsetOf - Return the current offset of the specified machine instruction /// getOffsetOf - Return the current offset of the specified machine instruction
@ -818,7 +818,7 @@ unsigned MipsConstantIslands::getOffsetOf(MachineInstr *MI) const {
// Sum instructions before MI in MBB. // Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?"); assert(I != MBB->end() && "Didn't find MI in its own basic block?");
Offset += TII->GetInstSizeInBytes(*I); Offset += TII->getInstSizeInBytes(*I);
} }
return Offset; return Offset;
} }
@ -1297,9 +1297,9 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex,
unsigned CPUIndex = CPUserIndex+1; unsigned CPUIndex = CPUserIndex+1;
unsigned NumCPUsers = CPUsers.size(); unsigned NumCPUsers = CPUsers.size();
//MachineInstr *LastIT = 0; //MachineInstr *LastIT = 0;
for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI); for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
Offset < BaseInsertOffset; Offset < BaseInsertOffset;
Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) { Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
assert(MI != UserMBB->end() && "Fell off end of block"); assert(MI != UserMBB->end() && "Fell off end of block");
if (CPUIndex < NumCPUsers && if (CPUIndex < NumCPUsers &&
CPUsers[CPUIndex].MI == static_cast<MachineInstr *>(MI)) { CPUsers[CPUIndex].MI == static_cast<MachineInstr *>(MI)) {
@ -1622,7 +1622,7 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
splitBlockBeforeInstr(*MI); splitBlockBeforeInstr(*MI);
// No need for the branch to the next block. We're adding an unconditional // No need for the branch to the next block. We're adding an unconditional
// branch to the destination. // branch to the destination.
int delta = TII->GetInstSizeInBytes(MBB->back()); int delta = TII->getInstSizeInBytes(MBB->back());
BBInfo[MBB->getNumber()].Size -= delta; BBInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent(); MBB->back().eraseFromParent();
// BBInfo[SplitBB].Offset is wrong temporarily, fixed below // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
@ -1644,14 +1644,14 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
.addMBB(NextBB); .addMBB(NextBB);
} }
Br.MI = &MBB->back(); Br.MI = &MBB->back();
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
// Remove the old conditional branch. It may or may not still be in MBB. // Remove the old conditional branch. It may or may not still be in MBB.
BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
MI->eraseFromParent(); MI->eraseFromParent();
adjustBBOffsetsAfter(MBB); adjustBBOffsetsAfter(MBB);
return true; return true;

4
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -602,7 +602,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
// Get instruction with delay slot. // Get instruction with delay slot.
MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 && if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 &&
DSI->isCall()) { DSI->isCall()) {
// If instruction in delay slot is 16b change opcode to // If instruction in delay slot is 16b change opcode to
// corresponding instruction with short delay slot. // corresponding instruction with short delay slot.
@ -692,7 +692,7 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
bool InMicroMipsMode = STI.inMicroMipsMode(); bool InMicroMipsMode = STI.inMicroMipsMode();
const MipsInstrInfo *TII = STI.getInstrInfo(); const MipsInstrInfo *TII = STI.getInstrInfo();
unsigned Opcode = (*Slot).getOpcode(); unsigned Opcode = (*Slot).getOpcode();
if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 && if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
(Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
Opcode == Mips::PseudoReturn)) Opcode == Mips::PseudoReturn))
continue; continue;

2
llvm/lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -398,7 +398,7 @@ bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
} }
/// Return the number of bytes of code the specified instruction may be. /// Return the number of bytes of code the specified instruction may be.
unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: default:
return MI.getDesc().getSize(); return MI.getDesc().getSize();

2
llvm/lib/Target/Mips/MipsInstrInfo.h
View File

@ -92,7 +92,7 @@ public:
virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
/// Return the number of bytes of code the specified instruction may be. /// Return the number of bytes of code the specified instruction may be.
unsigned GetInstSizeInBytes(const MachineInstr &MI) const; unsigned getInstSizeInBytes(const MachineInstr &MI) const;
void storeRegToStackSlot(MachineBasicBlock &MBB, void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,

2
llvm/lib/Target/Mips/MipsLongBranch.cpp
View File

@ -179,7 +179,7 @@ void MipsLongBranch::initMBBInfo() {
// Compute size of MBB. // Compute size of MBB.
for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin(); for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();
MI != MBB->instr_end(); ++MI) MI != MBB->instr_end(); ++MI)
MBBInfos[I].Size += TII->GetInstSizeInBytes(*MI); MBBInfos[I].Size += TII->getInstSizeInBytes(*MI);
// Search for MBB's branch instruction. // Search for MBB's branch instruction.
ReverseIter End = MBB->rend(); ReverseIter End = MBB->rend();

4
llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -108,7 +108,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
unsigned BlockSize = 0; unsigned BlockSize = 0;
for (MachineInstr &MI : *MBB) for (MachineInstr &MI : *MBB)
BlockSize += TII->GetInstSizeInBytes(MI); BlockSize += TII->getInstSizeInBytes(MI);
BlockSizes[MBB->getNumber()] = BlockSize; BlockSizes[MBB->getNumber()] = BlockSize;
FuncSize += BlockSize; FuncSize += BlockSize;
@ -155,7 +155,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
Dest = I->getOperand(0).getMBB(); Dest = I->getOperand(0).getMBB();
if (!Dest) { if (!Dest) {
MBBStartOffset += TII->GetInstSizeInBytes(*I); MBBStartOffset += TII->getInstSizeInBytes(*I);
continue; continue;
} }

2
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -11243,7 +11243,7 @@ unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
uint64_t LoopSize = 0; uint64_t LoopSize = 0;
for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I) for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J) { for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J) {
LoopSize += TII->GetInstSizeInBytes(*J); LoopSize += TII->getInstSizeInBytes(*J);
if (LoopSize > 32) if (LoopSize > 32)
break; break;
} }

2
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -1808,7 +1808,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
/// GetInstSize - Return the number of bytes of code the specified /// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes. /// instruction may be. This returns the maximum number of bytes.
/// ///
unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
unsigned Opcode = MI.getOpcode(); unsigned Opcode = MI.getOpcode();
if (Opcode == PPC::INLINEASM) { if (Opcode == PPC::INLINEASM) {

2
llvm/lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -256,7 +256,7 @@ public:
/// GetInstSize - Return the number of bytes of code the specified /// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes. /// instruction may be. This returns the maximum number of bytes.
/// ///
unsigned GetInstSizeInBytes(const MachineInstr &MI) const; unsigned getInstSizeInBytes(const MachineInstr &MI) const;
void getNoopForMachoTarget(MCInst &NopInst) const override; void getNoopForMachoTarget(MCInst &NopInst) const override;