OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 2
Code Issues Packages Projects Releases Wiki Activity

[RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins 

Add extension macro __riscv_zvlsseg to enable Zvlsseg builtins only
with target feature Zvlsseg.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D105626
This commit is contained in:
jacquesguan 2021-07-09 13:15:45 +08:00 committed by Ben Shi
parent 62cc3cdda6
commit 88326bbce3
5 changed files with 29 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
View File

@ -2,12 +2,14 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

10
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
View File

@ -2,12 +2,14 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

10
clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
View File

@ -2,12 +2,14 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

10
clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
View File

@ -2,12 +2,14 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

5
clang/utils/TableGen/RISCVVEmitter.cpp
View File

@ -141,6 +141,7 @@ enum RISCVExtension : uint8_t {
D = 1 << 2,
Zfh = 1 << 3,
Zvamo = 1 << 4,
Zvlsseg = 1 << 5,
};
// TODO refactor RVVIntrinsic class design after support all intrinsic
@ -784,6 +785,8 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
}
if (RequiredExtension == "Zvamo")
RISCVExtensions |= RISCVExtension::Zvamo;
if (RequiredExtension == "Zvlsseg")
RISCVExtensions |= RISCVExtension::Zvlsseg;
// Init OutputType and InputTypes
OutputType = OutInTypes[0];
@ -1237,6 +1240,8 @@ bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
OS << LS << "defined(__riscv_zfh)";
if (Extents & RISCVExtension::Zvamo)
OS << LS << "defined(__riscv_zvamo)";
if (Extents & RISCVExtension::Zvlsseg)
OS << LS << "defined(__riscv_zvlsseg)";
OS << "\n";
return true;
}