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[GlobalISel][AArch64] Fix pcsections for expanded atomics and add more tests 

Add fix for propagation of !pcsections metadata for expanded atomics,
together with more tests for interesting atomic instructions (based on
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll).

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D133710
This commit is contained in:
Marco Elver 2022-09-15 10:36:11 +02:00
parent 70ac466676
commit 72e7575ffe
4 changed files with 1335 additions and 4 deletions
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1
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
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@ -985,6 +985,7 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
TII->get(Opcode), MI.getDebugLoc(), /*NoImplicit=*/true);
MBB.insert(MBBI, NewMI);
MachineInstrBuilder MIB1(MF, NewMI);
MIB1->setPCSections(MF, MI.getPCSections());
MIB1.addReg(MI.getOperand(0).getReg(), RegState::Define)
.add(MI.getOperand(1))
.add(MI.getOperand(2))

4
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
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@ -2341,10 +2341,10 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) {
}
case TargetOpcode::G_FENCE: {
if (I.getOperand(1).getImm() == 0)
BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CompilerBarrier))
BuildMI(MBB, I, MIMetadata(I), TII.get(AArch64::CompilerBarrier))
.addImm(I.getOperand(0).getImm());
else
BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::DMB))
BuildMI(MBB, I, MIMetadata(I), TII.get(AArch64::DMB))
.addImm(I.getOperand(0).getImm() == 4 ? 0x9 : 0xb);
I.eraseFromParent();
return true;

1330
llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll Normal file
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File diff suppressed because it is too large Load Diff

4
llvm/test/CodeGen/AArch64/pcsections.ll
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@ -81,7 +81,7 @@ define i64 @test_complex_atomic() {
; CHECK-UNOPT-NEXT: stlxr
; CHECK-UNOPT: .Lpcsection9:
; CHECK-UNOPT-NEXT: cbnz
; CHECK-UNOPT: .Lpcsection12:
; CHECK-UNOPT: .Lpcsection13:
; CHECK-UNOPT-NEXT: b
; ---
; CHECK-NOT: .Lpcsection
@ -100,7 +100,7 @@ define i64 @test_complex_atomic() {
; CHECK-NEXT: .Lpcsection_base7:
; DEFCM-NEXT: .word .Lpcsection5-.Lpcsection_base7
; LARGE-NEXT: .xword .Lpcsection5-.Lpcsection_base7
; CHECK-UNOPT: .word .Lpcsection12-.Lpcsection_base14
; CHECK-UNOPT: .word .Lpcsection13-.Lpcsection_base15
; CHECK-NEXT: .text
entry:
%0 = atomicrmw add i64* @foo, i64 1 monotonic, align 8, !pcsections !0