[VENTUS][RISCV][feat] Add exception handler to stop spike in crt0.s

libclc/riscv32/lib/crt0.S

@@ -44,7 +44,7 @@ _start:
   csrr sp, CSR_LDS      # sp points to baseaddr of local memory of each SM
   # TODO: after we complete the stack adjustment for tp
   # change below code into addi tp, x0, 0
-  csrr tp, CSR_PDS        # tp points to baseaddr for lower bound of private memory(1K) of each thread
+  csrr tp, CSR_PDS      # tp points to baseaddr for lower bound of private memory(1K) of each thread
 
   # clear BSS segment
   la      a0, _edata
@@ -56,16 +56,18 @@ _start:
   bltu    a0, a2, 1b
 
 2:
-  csrr t0, CSR_KNL	      # get addr of kernel metadata
-  lw t1, KNL_ENTRY(t0)    # get kernel program address
-  lw a0, KNL_ARG_BASE(t0) # get kernel arg buffer base address
-  lw t2, KNL_PRINT_ADDR(t0) # get kernel print buffer address
-  lw t3, KNL_PRINT_SIZE(t0) # get kernel print buffer size
+  csrr t0, CSR_KNL	                 # get addr of kernel metadata
+  lw t1, KNL_ENTRY(t0)               # get kernel program address
+  lw a0, KNL_ARG_BASE(t0)            # get kernel arg buffer base address
+  lw t2, KNL_PRINT_ADDR(t0)          # get kernel print buffer address
+  lw t3, KNL_PRINT_SIZE(t0)          # get kernel print buffer size
   la t4, BUFFER_ADDR
   la t5, BUFFER_SIZE
   sw t2, 0(t4)
   sw t3, 0(t5)
-  jalr t1                 # call kernel program
+  la t6, spike_end                   # exception to stop spike
+  csrw mtvec, t6
+  jalr t1                            # call kernel program
 
   # call exit routine
   # tail    exit