[VENTUS][RISCV][feat] Add exception handler to stop spike in crt0.s

2023-04-27 10:19:21 +08:00 · 2023-04-27 10:19:21 +08:00 · 724033f20a
parent 5f776bde21
commit 724033f20a
1 changed files with 9 additions and 7 deletions
--- a/libclc/riscv32/lib/crt0.S
+++ b/libclc/riscv32/lib/crt0.S
@ -65,6 +65,8 @@ _start:
  la t5, BUFFER_SIZE
  sw t2, 0(t4)
  sw t3, 0(t5)
+  la t6, spike_end                   # exception to stop spike
+  csrw mtvec, t6
  jalr t1                            # call kernel program

  # call exit routine