[VENTUS][RISCV][feat] Add exception handler to stop spike in crt0.s
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@ -44,7 +44,7 @@ _start:
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csrr sp, CSR_LDS # sp points to baseaddr of local memory of each SM
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csrr sp, CSR_LDS # sp points to baseaddr of local memory of each SM
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# TODO: after we complete the stack adjustment for tp
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# TODO: after we complete the stack adjustment for tp
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# change below code into addi tp, x0, 0
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# change below code into addi tp, x0, 0
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csrr tp, CSR_PDS # tp points to baseaddr for lower bound of private memory(1K) of each thread
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csrr tp, CSR_PDS # tp points to baseaddr for lower bound of private memory(1K) of each thread
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# clear BSS segment
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# clear BSS segment
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la a0, _edata
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la a0, _edata
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@ -56,16 +56,18 @@ _start:
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bltu a0, a2, 1b
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bltu a0, a2, 1b
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2:
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2:
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csrr t0, CSR_KNL # get addr of kernel metadata
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csrr t0, CSR_KNL # get addr of kernel metadata
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lw t1, KNL_ENTRY(t0) # get kernel program address
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lw t1, KNL_ENTRY(t0) # get kernel program address
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lw a0, KNL_ARG_BASE(t0) # get kernel arg buffer base address
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lw a0, KNL_ARG_BASE(t0) # get kernel arg buffer base address
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lw t2, KNL_PRINT_ADDR(t0) # get kernel print buffer address
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lw t2, KNL_PRINT_ADDR(t0) # get kernel print buffer address
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lw t3, KNL_PRINT_SIZE(t0) # get kernel print buffer size
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lw t3, KNL_PRINT_SIZE(t0) # get kernel print buffer size
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la t4, BUFFER_ADDR
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la t4, BUFFER_ADDR
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la t5, BUFFER_SIZE
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la t5, BUFFER_SIZE
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sw t2, 0(t4)
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sw t2, 0(t4)
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sw t3, 0(t5)
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sw t3, 0(t5)
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jalr t1 # call kernel program
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la t6, spike_end # exception to stop spike
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csrw mtvec, t6
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jalr t1 # call kernel program
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# call exit routine
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# call exit routine
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# tail exit
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# tail exit
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