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[VENTUS][RISCV][feat] Add exception handler to stop spike in crt0.s

This commit is contained in:
zhoujingya 2023-04-27 10:19:21 +08:00
parent 5f776bde21
commit 724033f20a
1 changed files with 9 additions and 7 deletions
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2
libclc/riscv32/lib/crt0.S
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@ -65,6 +65,8 @@ _start:
la t5, BUFFER_SIZE la t5, BUFFER_SIZE
sw t2, 0(t4) sw t2, 0(t4)
sw t3, 0(t5) sw t3, 0(t5)
la t6, spike_end # exception to stop spike
csrw mtvec, t6
jalr t1 # call kernel program jalr t1 # call kernel program
# call exit routine # call exit routine